Nxp Usa, Inc.

Freescale Semiconductor,inc.

Benny Michalovich

Eran Glickman

Ron Michael Bar

Ron-Michael Bar

Nir Atzmon

Dmitriy Shurin

Idan Ben Ami

An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Method and apparatus for offloading functional data from an interconnect component

A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system is described. The controller comprises a hardware processor arranged to: receive a plurality of SATA data frames; identify a first primitive sequence in at least one of the plurality of SATA data frames that adversely affects a performance of the SATA system; and replace the identified first primitive sequence with a second primitive sequence in response thereto.

Controller, SATA system and method of operation therefor

A layered network () to provide offload of data in a communication processor (). The layered network () includes a first set (S) of network elements at a first layer (L) and a second set (S) of one or more network elements at a second layer (L). The network elements of the first set (S) are configured for processing incoming data and the network elements of the second set (S) of one or more network elements at the second layer (L) are configured to process intermediate data received from the first set (S) of network elements. The network elements of a particular subset (S) of the network elements of the first set (S) of network elements are connected to only a particular network element (E) of the second set (S) to transfer the incoming data processed by the network elements of the particular subset (S) to the particular network element (E) of the second set (S). The layered network () further includes a powering controller () configured to, during offload of the data, put a particular network element (E) of the second set (S) at the second layer (L) in an on state only if at least a particular network element (E) of the particular subset (S) of the network elements of the first set (S) at the first layer (L) is in an on state and at least one of the network elements of the first set (S) is in an off state. The powering controller () is configured to discriminate between chains of network elements formed by at least network elements of the first set (S) and network elements of the second set (S) and to have a chain in an on state if a first network element of the chain at a highest layer hierarchy is in an on state.

Selectively powered layered network and a method thereof

A data processing device comprises a protection key unit, a dummy key unit, and a control unit. The protection key unit provides a protection key. The dummy key unit provides a dummy key. The dummy key unit has a set of two or more allowed dummy key values associated with it and is configurable by a user or a host device to set the dummy key to any value selected from said set of allowed dummy key values. The control unit is connected to the dummy key unit and to the protection key unit and arranged to set the protection key to the value of the dummy key in response to a tamper detection signal (fatal_sec_vio) indicating a tamper event. The value of the dummy key may notably be different from zero. A method of protecting a data processing device against tampering is also described.

Data processing device and method for protecting a data processing device against tampering

An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command.

Integrated circuit device, data storage array system and method therefor

A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers. A method of operating a system on chip is also described.

System on chip and method of operating a system on chip

A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral. A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect busand which comprises a conversion table with translation information. The AAis configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.

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Raanana, Israel

Benny Michalovich