Lattice Semiconductor Corporation

Btr Limited

Benny Ma

Om P Agrawal

Benjamin S Ting

Ju Shen

Peter M Pani

Cyrus Y Tsui

San-Ta Kow

Jack Tim Wong

Chan-Chi Jason Cheng

Ann Wu

Sam Tsai

Clement Lee

Thomas Tsui

In one embodiment, a data decompression circuit for a data stream having a repeated data word is provided. The data stream is compressed into a series of data frames such that the repeated data word is removed from the series of data frames and such that each data frame corresponds to a header. The circuit includes a decompression engine configured to decompress each data frame into a corresponding decompressed data frame, the decompression engine being further configured to decode each header to identify whether word locations in the corresponding decompressed data frame should be filled with the repeated data word.

Data decompression

An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.

Non-volatile and reconfigurable programmable logic devices

In a programmable integrated circuit, a discharge circuit for discharging high voltage nodes provides a current path whose current is limited by a control voltage. In one embodiment, the current path is implemented by a transistor coupled to the high voltage nodes, with the control voltage provided by a current mirror coupled to the current path. The control voltage is applied across the gate and source terminals of the transistor. In one embodiment, the source terminal of the transistor is precharged to a supply voltage less a threshold voltage of a transistor. With the current in the current path thus limited, threshold voltage shifts and other damages to the functional circuit of the integrated circuit due to the discharge current of high voltage nodes are avoided.

Current-controlled high voltage discharge scheme

A programmable logic device having an internal tristate bus is provided. The internal tristate bus may be driven by a plurality of driving elements. Such a tristate bus, and the circuitry for supporting it, can be implemented on less surface area than the multitude of unidirectional buses, and supporting circuitry, which would otherwise be required for the same plurality of driving elements. Accordingly, the amount of surface area that is required to move information within a programmable logic device is reduced. Furthermore, in one embodiment, a arbitration logic circuit is provided for each driving element. These arbitration logic circuits cooperate to prevent the different elements from simultaneously driving the internal tristate bus. Accordingly, the integrity of the information on such bus is maintained.

Internal tristate bus with arbitration logic

In a programmable integrated circuit, by providing a static random access memory (SRAM) cell in each electrically erasable (E.sup.2) non-volatile memory cell, testing time of circuits configured by the E.sup.2 non-volatile memory cells can be reduced substantially. In one embodiment, the SRAM cell can be included by providing a small number of transistors to recirculate the output value of an inverting buffer. During testing, a logic value is written into the SRAM cell in place of the logic value in the non-volatile storage of the E.sup.2 non-volatile memory cell. In one embodiment, the E.sup.2 non-volatile memory cell can be used in conjunction with a 1-bit shift-register. Multiple 1-bit shift registers can be used as a scan chain to scan into the SRAM cells of multiple E.sup.2 non-volatile memory cells.

Electrically erasable non-volatile memory cell with integrated SRAM cell

An electrically erasable non-volatile memory cell dissipates virtually no power by disabling a pull-up current when the non-volatile memory cell is programmed. In one embodiment, to properly initialize the electrically erasable non-volatile memory cell, the power of an inverting output buffer is provided only after the pull-up circuit substantially completes pulling up an input terminal of the inverting output buffer. In one embodiment, the electrically erasable non-volatile memory cell is used in a programmable integrated circuit.

Electrically erasable non-volatile memory cell with no static power

A bidirectional passgate switch for connecting two conductors utilizes technology such as electrically erasable programmable read only memory (EEPROM). The switch includes two EEPROM components wherein the floating gates of the components are shared. In one embodiment a first n-channel passgate transistor is used for programming and storage of the state of the switch. The oxide of the first transistor is a thin oxide to enable ease of programming. A second n-channel passgate transistor functions as the bidirectional switch wherein the source and drain terminals are coupled to the routing lines to be selectively connected. The second transistor oxide is a thick oxide to minimize the leakage due to tunneling. Thus, the programming lines and routing lines are separated, making the programming process simpler while minimizing leakage.

Growing community of inventors

Saratoga, CA, United States of America

Benny Ma