Sun Microsystems, Inc.

Bennet H Ih

Glenn A Dearth

Paul M Whittemore

George R Plouffe, Jr

David A Medeiros

Jorge E Lach

The present invention is directed to a system having a shared processing resource, a plurality of processing modules and a synchronization control module. The shared processing resource is configured to perform processing operations in connection with input data provided by the processing modules, in response to a start indication. Each of the processing modules is configured to perform selected processing operations. At least one of the processing modules is configured to provide input data to the shared processing resource. Each processing module that provides input data is configured to generate a hold indication and to provide the input data to the shared processing resource in response to a synchronization barrier lock. Each processing module is configured to generate a start enable indication. Each processing module that provides input data generates a start enable indication after providing the input data. At least one of the processing modules further is configured to generate the start indication for the shared processing resource. The synchronization control module being provides, in response to each hold indication from one of the processing modules, a synchronization barrier lock for enabling one of the processing modules to provide input data to the shared processing resource.

Interface for interfacing simulation tests written in a high-level programming language to a simulation model

A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment element. The plurality of circuit elements define a plurality of clock domains, and circuit elements in each clock domain perform processing operations under control of a respective domain clock signal. The scan chain establishment element interconnects the circuit elements in a scan chain to facilitate loading and/or retrieval of a scan vector into and/or out of the digital circuit device. The unitary clock domain establishment element establishes a unitary clock domain for the circuit element when the scan chain establishment element is interconnecting the circuit elements in a scan chain. Thus, the scan vector will be loaded into or retrieved from the digital electronic circuit device using the single, unitary clock signal, thereby avoiding any necessity of using synchronizers or other elements for the scan chain which can complicate layout of the device.

System and method for providing scan chain for digital electronic device

A base test class is defined in an object-oriented computer program development environment and members of the base test class, i.e., test objects, represent individual test processes in a computer. The base test class defines a number of attributes and member functions which are inherited by test objects including a constructor member function which is performed when a test object is created. Creation of a test object performs substantially all that is required to implement interfaces and protocols (i) for interaction between the test object and simulation systems, (ii) for synchronization of processing of the test object with processing of other test objects and with simulation systems, and (iii) for reservation by the test object of devices of simulation systems. In addition, a base device class defines a number of attributes and member functions which are inherited by device objects. Device objects represent devices of simulation systems which interact with the test process. The base device class defines read and write member functions which invoke test member functions to transfer of data between the test object and a simulation system and a device constructor member function such that merely creating a device object automatically reserves the device represented by the device object to the test object within which the device object is created. In addition, by merely deleting the device object, reservation of the represented device is automatically released.

Object-oriented development framework for distributed hardware simulation

An interface subsystem for use in a system including one or more simulation systems facilitates simulation of one or more simulation models under control of one or more tests. The interface subsystem allows the tests and simulation systems to transfer information therebetween and enables said tests to control the simulation systems in simulating the simulation model during a simulation run. The simulation systems include transactors which provide information to the simulation model at the beginning of a simulation run, pause a simulation run in response to detection of a selected event, and generate simulation result information. The interface subsystem includes, associated with each test, a simulation information generator, a simulation control indicator generator, and a information receiver; associated with each simulation system an information receiver associated with each transactor and a simulator interface module; and an interface core. The a simulation information generator provides simulation information to be transferred to said simulation system for use during a simulation run and the simulation control indicator generator generates a simulation control indicator for controlling said simulation system. Each test's information receiver receives simulation result information generated during a simulation run. Each simulation system's simulator interface module (a) receives simulation information and providing the received simulation to an information receiver for use by the associated transactor, (b) receives simulating result information from said at least one transactor to be provided to said at least one test, and (c) controls said at least one simulation system to initiate a simulation run in response to receipt of a control indicator. Each transactor's information receiver receives simulation information for use by the associated transactor during a simulation run. The interface core transfers (a) simulation information from a test to the simulator interface module of a simulating system for provision to one transactor's information receiver for use by a transactor during a simulation run, (b) said simulation control indicator to the simulator interface module of a simulation system for controlling the simulation system in a simulation run, and (c) simulation result information from the transactors to the tests during a simulation run.

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Cambridge, MA, United States of America

Bennet H Ih