Imec

Globalfoundries Inc.

Intel Corporation

Benjamin Vincent

Voon Yew Thean

Geert Eneman

Roger Loo

David Paul Brunco

Matty Caymax

Geert Hellings

Liesbeth Witters

Avi Feshali

Andriy Hikavyy

Johan Dekoster

Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.

Methods and mask structures for substantially defect-free epitaxial growth

Techniques and mechanisms for providing efficient direction of light to a photodetector with a tapered waveguide structure. In an embodiment, a taper structure of a semiconductor device comprises a substantially single crystalline silicon. A buried oxide underlies and adjoins the monocrystalline silicon of the taper structure, and a polycrystalline Si is disposed under the buried oxide. During operation of the semiconductor device light is redirected in the taper structure and received via a first side of a Germanium photodetector. In another embodiment, one or more mirror structures positioned on a far side of the Germanium photodetector may provide for a portion of the light to be reflected back to the Germanium photodetector.

Photodetector with tapered waveguide structure

Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.

Methods using mask structures for substantially defect-free epitaxial growth

A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

FinFET device with dual-strained channels and method for manufacturing thereof

Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer.

Method for producing strained Ge fin structures

Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.

Method for selective growth of highly doped group IV&#x2014;Sn semiconductor materials

A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

Methods for manufacturing semiconductor devices

The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted 'V' band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Band engineered semiconductor device and method for manufacturing thereof

The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted 'V' band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl). The tin-tetrachloride inhibits the deposition of the second semiconductor material on the insulator material of the second region.

Method for selective deposition of a semiconductor material

The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a non-reactive carrier gas and a higher order germanium precursor gas, i.e. of higher order than germane (GeH), is applied. In an example embodiment, the deposition is done under application of a deposition temperature between 275&#xb0; C. and 500&#xb0; C., with the partial pressure of the precursor gas within the mixture being at least 20 mTorr for temperatures between 275&#xb0; C. and 285&#xb0; C., and at least 10 mTorr for temperatures between 285&#xb0; and 500&#xb0; C.

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San Francisco, CA, United States of America

Benjamin Vincent