Sofics Bvba

Sarnoff Corporation

Sarnoff Europe

Sarnoff Europe Bvba

Benjamin Van Camp

Bart Sorgeloos

Sven Van Wijmeersch

Olivier Marichal

Geert Wybo

Stefaan Verleye

Wim Vanhouteghem

Bart Keppens

Johan Van Der Borght

Gerd Vermont

John Armer

Markus Paul Josef Mergens

Koen Gerard Maria Verhaege

Phillip Czeslaw Jozwiak

Steven Thijs

Pieter Vanysacker

Frederic Marie Dominique De Ranter

Frederic De Ranter

Wybo Geert

Oliver Marichal

Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.

Semiconductor device for electrostatic discharge protection

An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Electrostatic discharge protection device

An electrostatic discharge (ESD) protection circuit is disclosed including at least a clamping device, a switching device, and a voltage limiter. The ESD protection circuit may include devices of different voltage domains. The switching device may be in series with the clamping device to block at least a portion of a voltage from dropping across the clamping device. The switching device may sustain higher maximum operating voltages than the clamping device.

High holding voltage, mixed-voltage domain electrostatic discharge clamp

An electrostatic discharge (ESD) protection device is disclosed. The ESD protection circuit is configured to operate in high voltage domains. The ESD protection device may further include stacked NMOS or PMOS devices. The gates of the MOS devices may be driven by respective inverters. The inverters may be coupled to a voltage divider and may be triggered by respective trigger circuits. Power nodes of the inverters may be connected such that devices in the ESD protection circuit are exposed to voltages that are within their maximum voltage rating.

Electrostatic discharge protection for high voltage domains

The present invention provides an ESD protection device having at least one diode in a well of first conductivity type formed in a substrate of second conductivity type. The circuit further includes a guard-band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between the diode cathode, the substrate and the guard-band.

Diode chain with guard-band

An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) having a first voltage potential, a first power supply potential and a second power supply potential. The ESD circuit includes a first NPN bipolar transistor having a first N-doped junction, a second N-doped junction and a third P-doped base junction. The first N-doped junction is coupled to the first voltage potential and the second N-doped junction is coupled to the first power supply potential. The ESD circuit also includes a first PNP bipolar transistor having a first P-doped junction, a second P-doped junction and a third N-doped base junction. The first P-doped junction is coupled to the first voltage potential and the second P-doped junction is coupled to the second power supply potential. The third P-doped base junction of the first NPN bipolar transistor is coupled to the third N-doped base junction of the first PNP bipolar transistor.

Electrostatic discharge protection

The present invention provides an ESD protection device having at least one diode in a well of a first conductivity type formed in a substrate of a second conductivity type. The circuit further includes a guard-band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between the diode cathode, the substrate and the guard-band.

Diode chain with a guard-band

The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.

Electrostatic discharge protection circuit

The present invention provides an ESD device to reduce the total triggering current without increasing the overshoot voltage. This is achieved by localizing the triggering current, such that the local current density remains high enough to trigger the ESD device. This localized triggering provides a fast and efficient triggering of the ESD device.

Localized trigger ESD protection device

The present invention provides an ESD protection circuitry in a semiconductor integrated circuit (IC) having protected circuitry to prevent false triggering of the ESD clamp. The circuitry includes an SCR as an ESD clamp having an anode adapted for coupling to a first voltage source, and a cathode adapted for coupling to a second voltage source. The circuitry also includes at least one noise current buffer (NCB) coupled between at least one of a first trigger tap of the SCR and the first voltage source such that the first trigger tap of the SCR is coupled to a power supply.

Electrostatic discharge protection structures with reduced latch-up risks

The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Bulk resistance control technique

The present invention provides a semiconductor structure device having a first and a second semiconductor devices with a silicon controlled rectifier (SCR) formed between the two devices with advantages to couple the devices to provide more design flexibility and enhanced triggering in order to improve the ESD performance of the device.

Growing community of inventors

Antwerp, Belgium

Benjamin Van Camp