Advanced Micro Devices Corporation

Ati Technologies Ulc

Intel Corporation

Benjamin Tsien

Alexander J Branover

John P Petry

Thomas James Gibney

Christopher T Weaver

Vydhyanathan Kalyanasundharam

Indrani Paul

Chintan S Patel

Mihir Shaileshbhai Doctor

Stephen Victor Kosonocky

Bryan P Broussard

Greggory D Donley

Pravesh Gupta

Ashish Jain

Oswin Hall

Philip Ng

William Alexander Hughes

Kevin Michael Lepak

Amit P Apte

Alan Dodson Smith

Gia Tung Phan

Denis Rystsov

Brannon J Batson

Shang Yang

William A Welch

Anthony Asaro

Richard Martin Born

Eric Christopher Morton

Jimshed B Mirza

Guhan Krishnan

Michael J Tresidder

Sonu Arora

Elliot H Mednick

Maggie Chan

Ann M Ling

Jun Lei

Dennis Au

Jonathan David Hauke

Vincent Cueva

Yaniv Adiri

Ivan Yanfeng Wang

Samuel D Naffziger

James Raymond Magro

Kiran Bondalapati

Eric M Rentschler

Patrick N Conway

Carl Kittredge Wakeland

Sebastien Nussbaum

Xiaojie He

Andrew William Lueck

Hui Zhou

Kostantinos Danny Christidis

Aaron Joseph Grenat

Ming L So

Narendra Kamat

Chen-Ping Yang

Sridhar Varadharajulu Gada

Dhirendra Partap Singh Rana

Xiao Gang Zheng

Dilip Kumar Jha

Hao Huang

Rostyslav Kyrychynskyi

Jeremy Schreiber

Edgar Munoz

MingLiang Lin

Joyce C Wong

Felix Ho

Joseph Scanlon

Sreenath Thangarajan

Jose G Cruz

Vamsi Krishna Alla

Bradley Kent

Greggory Douglas Donley

The disclosed device includes a heterogeneous processor architecture having heterogeneous processors, and a control circuit that can assign, in response to an interrupt, the interrupt to one of the heterogenous processors that is selected based on power efficiency. Various other methods, systems, and computer-readable media are also disclosed.

Arbitrated interrupt steering in heterogeneous processors

Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. In order to reduce visual artifacts that may occur while the memory accesses are blocked, a memory subsystem includes a control circuit configured to enable a caching mode which caches display data provided to the display controller. Subsequent requests for display data from the display controller are then serviced using the cached data instead of accessing memory.

Memory power performance state optimization during image display

A method, system, and apparatus determines whether a task should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. The task is relocated from the first processor to the second processor and executed on the second processor based on the comparing.

Method of task transition between heterogenous processors

The disclosed device includes multiple mesh lanes for sending data packets across the device. The device also includes a control circuit that can detect a low bandwidth workload and reroute data packets to avoid one or more mesh lane. The control circuit can then disable the avoided mesh lanes. Various other methods, systems, and computer-readable media are also disclosed.

Reduced mesh lane routing

Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. To sustain a desired quality of service for the display, a display controller is configured to prefetch data in advance of the performance-state change. In order to ensure the display controller has sufficient memory bandwidth to accomplish the prefetch, bandwidth reduction circuitry in clients of the system are configured to temporarily reduce memory bandwidth of corresponding clients.

On-demand regulation of memory bandwidth utilization to service requirements of display

The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media are also disclosed.

Low power memory state during non-idle processor state

Systems, apparatuses, and methods for efficient power management of a multi-node computing system are disclosed. A computing system includes multiple nodes that receive tasks to process. The nodes include a processor, local memory, a power controller, and multiple link interfaces for transferring messages with other nodes across links. Using a distributed approach for power management, negotiation for powering down components of the computing system occurs without performing a centralized system-wide power down. Each node is able to power down its links, its processor and other components regardless of whether other components of the computing system are still active or powered up. A link interface initiates power down of a link with delay or without delay based on a prediction of whether a link idle condition leads to the link interface remaining idle for at least a target idle threshold period of time.

Mechanism for performing distributed power management of a multi-GPU system by powering down links based on previously detected idle conditions

Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

System-wide low power management

Systems and methods are disclosed for scheduling a data link training by a controller. The system and method include receiving an indication that a physical layer of a data link is not transferring data and initiating a training process of the physical layer of the data link in response to the indication that the physical layer of the data link is not transferring data. In one aspect, the indication that the physical layer of a data link is not transferring data is an indication that the physical layer of the data link is in a low power state. In another aspect, the indication that the physical layer of a data link is not transferring data is an indication that a data transfer has been completed.

Scheduling training of an inter-chiplet interface

Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

On-demand IP initialization within power states

Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.

Device and method for two-stage transitioning between reduced power states

A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.

Method and apparatus for managing power states

A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

Last level cache access during non-Cstate self refresh

Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the physical layer.

Droop mitigation for an inter-chiplet interface

A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.

Data fabric C-state management

Growing community of inventors

Fremont, CA, United States of America

Benjamin Tsien