Stmicroelectronics (Research & Development) Limited

Stmicroelectronics Gmbh

Benjamin Thomas Sarachi

Sergio Miguez Aparicio

Jeffrey M Raynor

Jeff M Raynor

In accordance with an embodiment, a system includes: a primary device configured to be connected to at least one secondary device via serial bus having a data wire and a clock wire. The primary device is configured to: provide a clock signal on the clock wire; and transmit a frame comprising control bits on the serial bus, wherein a number of control bits transmitted on the serial bus at at least one location of the frame indicates a format of the frame.

Serial bus protocol

The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.

Growing community of inventors

Edinburgh, United Kingdom

Benjamin Thomas Sarachi