Primarion Corporation

Infineon Technologies Austria Ag

Northrop Grumman Systems Corporation

Benjamin Tang

Kenneth A Ostrom

Scott Wilson Southwell

Keith Nelson Bassett

Robert T Carroll

Tim Ng

Nicholas Robert Steffen

Richard Pierson

Mattia Oddicini

Sue Perranoski

Ken Ostrom

Timothy M Ng

Darryl Tschirhart

Hongying Ding

Hamid Behjati Najafabadi

Jinghong Guo

Herbert Zojer

An apparatus for generating an applicable control signal, including: a control module operable to generate a reference control signal that avoids, but is effectively within, a forbidden region by alternating the reference control signal between upper and lower levels of the forbidden region; an error determination module operable to generate an error signal based on a difference between the reference control signal and the applicable control signal; and a compensation module operable to noise-shape the error signal to suppress a portion of the error signal resulting from avoiding the forbidden region, and to modify the reference control signal based on the noise-shaped error signal, wherein the modified reference control signal is output by the apparatus as the applicable control signal for generating a modulation signal.

Modulation signal generation avoiding forbidden regions

A system for balancing current supplied by a plurality of regulators coupled to a load includes circuitry operable to measure an average load current supplied by each regulator, determine an overall average current to be shared by the plurality of regulators, and compare each average load current with the overall average current to be shared by the plurality of regulators. The circuitry included in the system is also operable to adjust an output current of one or more of the plurality of regulators so that the plurality of regulators supply the same current to the load.

System for balancing current supplied to a load

A method of balancing current supplied by a plurality of regulators coupled to a load includes: measuring an average load current supplied by each regulator; determining an overall average current to be shared by the plurality of regulators; comparing each average load current with the overall average current to be shared by the plurality of regulators; and adjusting an output current of one or more of the plurality of regulators so that the plurality of regulators supply the same current to the load.

Method of balancing current supplied to a load

A multiphase power regulator includes a multiphase pulse width modulator, an output stage and an active transient response circuit. The output stage includes a high side transistor, a low side transistor and an inductor. The output stage is configured to supply power to a load responsive to signals generated by the multiphase pulse width modulator. The active transient response circuit is coupled between the output stage and the multiphase pulse width modulator and configured to detect the voltage level at the output stage and provide a signal to the multiphase pulse width modulator that is a function of the amplitude of the deviation of the detected voltage level from a target voltage.

Multiphase power regulator with active transient response circuitry

Methods and apparatus for power supply load dump compensation according to various aspects of the present invention may operate in conjunction with a power stage system, such as a power stage system comprising a bootstrapped driver circuit and a power stage responsive to the driver circuit. The power stage system may further include a load dump compensation circuit connected to the driver circuit, wherein the load dump compensation circuit is configured to remove a bias current generated by the bootstrapped driver circuit. Various aspects of the present invention may be implemented in conjunction with any appropriate power supply, such as a switching regulator, for example a buck converter.

Methods and apparatus for power supply load dump compensation

Methods and apparatus for current sensing in mutually coupled inductors according to various aspects of the present invention may operate in conjunction with a control system adapted to control current through the inductors and multiple current sensors connected to the control system. Each current sensor may comprise a series combination comprising a capacitor and a resistor. The series combination may be connected in parallel with one of the inductors, and may be adapted to generate branch inductor current signals according to a sensed current in the connected inductor. In addition, a coupling capacitor may be coupled between at least two of the current sensors to compensate a time constant of the current sensor for mutual coupling inductance between the inductors.

Methods and apparatus for current sensing in mutually coupled inductors

Disclosed is a multi-phase pulse width modulated voltage regulator and method in which transient voltage excursions or deviations that exceed the load line voltage by more than a pre-determined amount are detected by an ATR circuit and a correction signal is applied. The correction signal is in the form of asynchronous pulses and the number of such pulses is a function of the magnitude of the voltage excursion as determined by the number of thresholds that are exceeded. Also disclosed is an adaptive voltage positioning (AVP) circuit and method for early detection of a transient event by sensing voltage changes at the load and adjusting the target voltage with pre-determined current values prior to the time that ATR event changes in the current at the load are detected.

Multi-threshold multi-gain active transient response circuit and method for digital multiphase pulse width modulated regulators

A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL, which represents a fill level of a FIFO. A granular FIFO fill level indicator of the DLL provides input to the phase shifter to adjust the frequency of the PLL accordingly. Thus, the frequency of the data input rate can be controlled and a constant fill level of the FIFO can be maintained. A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator

Disclosed is a fine resolution pulse width generator for use in a multiphase pulse width modulated voltage regulator. The fine pulse width is generated by first generating a pulse with a coarse pulse width and one or more delayed replicas thereof. Then, digitally controlled analog interpolators are used to generate the fine resolution pulse width pulse by interpolating among the coarse pulse width pulses. Both single edge and double edge modulation embodiments are disclosed providing interpolation of just the trailing edges of the coarse pulses or both the leading and trailing edges, respectively. The disclosed fine resolution pulse generator uses counters, thermometer encoders and analog interpolators to achieve interpolation accurately by insuring that each interpolation step corresponds to an equal weight. Accuracy of the interpolation is defined by the linearity (i.e. how well the interpolation fits a best fit straight line) and monotonicity (i.e. how each step contributes a positive weight to the total).

Fine resolution pulse width modulation pulse generator for use in a multiphase pulse width modulated voltage regulator

A method, apparatus, and system for routing signals in a microelectronic device are disclosed. The system includes a plurality of chip components, such as transient suppression regulators, that are configured to include a transmission path that is routed through the chip component for transmission of any signal, for example, a signal from a communication bus of the microelectronic device.

Power, ground, and routing scheme for a microprocessor power regulator

A serial bus control method, apparatus, and system for transmitting signals between a master controller and a slave controller associated with a power regulator are disclosed. The serial bus control scheme allows for information to be written to or read from individual regulators or be written to read from all regulators that are coupled to the master controller.

Serial bus control method and apparatus for a microelectronic power regulation system

An apparatus and method for detecting the presence of a valid signal includes an offset generator coupled to a pair of data slicers and an XOR gate. The offset generator is configured to both add and subtract a predetermined voltage to an input voltage in its two outputs. The two outputs of the offset generator are both compared to a predetermined value in a pair of data slicers. If the outputs of the data slicers are the same (i.e., either both offset signals are positive or both are negative), then a valid signal is indicated.

Method and apparatus for detecting valid signal information

A sense circuit and a system including a sense circuit are disclosed. The sense circuit is configured to measure and change in current with respect to time and/or a change in voltage across a portion of a substrate.

Method apparatus, and system for sensing a power change during operation of a microelectronic device

The present invention is directed to an improved system and method for transmitting and receiving digital data. In order to counter the spatial filtering effects of a digital data bus, data is spatially filtered by a driver before being sent on the digital data bus to its destination. In the alternative, the data may be spatially filtered by a receiver after being sent on the digital data bus. The spatial filter may include one or more current-limiting elements, such as a resistor or a transistor, coupled between the power supply and the various buffers on the bus. Such a configuration results in a lowering of the crosstalk and ground bounce present between adjacent lines on a data bus.

Spatially filtered data bus drivers and receivers and method of operating same

The present invention includes a system and method for improving phase selection using a phase selector system. An exemplary phase selector system of the present invention includes a high speed phase selector having control logic, XOR gates, and a selector. The control logic uses Gray coding to generate one or more control signals. For example, the control logic uses a 3 bit word to select a phase for clock recovery. A selector coupled to the control logic determines the phase selected. XOR gates coupled between the control logic and the selector provide eight phases of a clock using four input phases of the clock with inversion. In this manner, a four to one selector can choose one of eight phases from the XOR gates to aid in clock recovery. The selector control logic has a continuous output phase during a change to an adjacent phase, which substantially prevents glitching on the clock.

Growing community of inventors

Rancho Palos Verdes, CA, United States of America

Benjamin Tang