John Fluke Mfg. Co., Inc.

Other

Fluke Corporation

Benjamin T Brodie

Henriecus Koeman

John D Witters

A multiple slope integrating analog-to-digital converter (ADC) includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to come as close as possible to nulling the voltage magnitude at the output of the integrator. A controller keeps track of the charge that has been added to and removed from the integrator during the integrate cycle, and provides a coarse conversion value. The residual voltage is de-integrated to provide a fine conversion value, which is added to the coarse conversion value to provide a final value. The switches which control selection of the positive and negative reference currents are implemented and operated in such a way that linear error due to current injected into the integrator is minimized, and increased conversion speed is exhibited. At any given time during the integrate cycle, only one switch at a time is ON.

Multiple slope analog-to-digital converter having increased linearity

An AC resistor attenuator with low parasitic capacitance coupling and, thus, a substantially constant attenuation value over a relatively wide frequency range is disclosed. The AC resistor attenuator comprises a first elongate resistor substantially entirely surrounded by a second elongate resistor. The first and second elongate resistors are thermally matched and have a substantially identical resistance profile. The first and second resistors are connected in series. The other ends of the first and second resistors are connected across the source of the signal to be attenuated. The attenuated signal is obtained at the junction between the first and second resistors. Except in the case where fifty percent (50%) attenuation is to be provided, the higher value resistance of the attenuator forms the first resistor and the lower value forms the second resistor. Preferably, the first resistor is a finely distributed thin film resistor on a suitable dielectric substrate; and, the second resistor is formed of two elements, each comprising a finely distributed thin film resistor on a suitable dielectric substrate. The two elements are mounted on opposite sides of the substrate supporting the first resistor. Alternative embodiments include further resistors positioned so as to surround the first and second resistors (and other inner resistors) in the same manner as the second resistor surrounds the first resistor. Regardless of form, the external resistors reduce parasitic capacitive coupling (i.e., coupling to surrounding items) to the inner resistors. As a result, the attenuation value remains the same over a wide frequency range. In addition to being used as a simple AC resistance attenuator, the AC resistor attenuator is also used in feedback and other amplifier systems to provide improved amplifier systems having an amplification value that remains constant over a relatively wide frequency range.

AC Resistor attenuator and associated amplifier circuits

A signal whose RMS value is to be accurately determined is first converted into DC form by a relatively inaccurate RMS converter, such as a thermal RMS converter (15). The result is a first converter signal (Y.sub.1), which is stored for recirculation in a suitable storage device, such as a sample and hold circuit (17). Thereafter, the signal stored in the storage device is recirculated to the converter to create a second converter signal (Y.sub.2). Then, the second converter signal is subtracted from the doubled value of the first converter signal (2Y.sub.1 -Y.sub.2) to produce a corrected RMS signal (X). The difference between the first converter signal (Y.sub.1) and the corrected RMS signal (X) is then determined. This error signal (E) is stored. Next, a decision is made as to whether or not a fast mode of operation is to be followed. If it is not to be followed the corrected RMS signal is displayed. If the fast mode is to be followed, the signal whose RMS value is to be accurately determined is reapplied to the RMS converter. The result is a third converter signal from which the error signal is subtracted to produce a corrected signal that accurately represents the RMS value of the reapplied signal. This corrected signal is then displayed or applied to other downstream subsystems, such as signal analyzers or recorders. The fast mode steps are then repeated.

Recirculating RMS AC conversion method and apparatus with fast mode

A sample and hold (S/H) circuit that produces an output signal having essentially zero offset voltage error is disclosed. The S/H circuit includes a pair of operational amplifiers (OA3 and OA4) that are connected in circuit during both the sample and the hold modes of operation. In the sample mode of operation one of the operational amplifiers (OA3) receives the incoming signal through a first resistor (R1) and in accordance therewith controls the magnitude of an inverted voltage stored on a storage capacitor (C1); and, the other operational amplifier (OA4) senses the stored inverted voltage and, in accordance therewith, applies a feedback voltage to the signal input of OA3 through a second resistor (R2). In the hold mode of operation OA4 senses the voltage stored on C1 and, in accordance therewith, via R2 and OA3 controls the output voltage, which has the correct polarity due to the inverted voltage being inverted by OA3. In addition, during the hold mode of operation, the output voltage is fed back through R1 to the input of OA3 receiving the output of OA4. If the resistance of R1 equals the resistance of R2, the magnitude of the voltage stored by C1 is equal to the input signal voltage. If the resistance ratio of R2 to R1 is greater than one, the magnitude of the stored voltage is greater than the input signal voltage, even though the output voltage is equal to the input signal voltage. Storing a higher level voltage reduces the effect of capacitor leakage and OA4 drawing current from C1 on the output voltage.

Sample and hold circuit

A signal whose RMS value is to be accurately determined is first converted into DC form by a relatively inaccurate RMS converter, such as a thermal RMS converter (15). The result is a first converter signal (Y.sub.1), which is stored for recirculation in a suitable device, such as a sample and hold circuit (17). The first converter signal is also doubled (2Y.sub.1) and stored (41). Thereafter the first converter signal stored in the storage device is recirculated to the converter to create a second converter signal (Y.sub.2). Then, the second converter signal is subtracted (43) from the doubled first converter (2Y.sub.1 -Y.sub.2) to produce a highly accurate RMS output signal.

Growing community of inventors

Edmonds, WA, United States of America

Benjamin T Brodie