Micron Technology Incorporated

Zeno Semiconductor, Inc.

Spin Memory, Inc.

Integrated Silicon Solution, (cayman) Inc.

Mosaid Technologies Corporation

Spin Transfer Technologies, Inc.

Round Rock Research, LLC

Conversant Intellectual Property Management Incorporated

Benjamin S Louie

Yuniarto Widjaja

Neal Berger

Jin-Woo Han

Lester Crudele

Aaron S Yip

Vinod C Lakhani

Mourad El-Baraji

Jin-Man Han

Daniel L Hillman

Hagop A Nazarian

Mourad El Baraji

Frankie F Roohparvar

Zvi Or-Bach

Dzung Huu Nguyen

Ali Mohammadzadeh

Susmita Karmakar

Hendrik Hartono

Ebrahim Abedifard

Adam D Johnson

Scott N Gatzemeier

Barry Hoberman

Christophe J Chevallier

Kuk-Hwan Kim

Yunqiu Wan

Judy Wan

Amitay Levi

Kadriye Deniz Bozdag

Wallace E Fister

Peter P Cuevas

TaeJin Pyon

Asim Bajwa

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

NAND string utilizing floating body memory cell

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Content addressable memory device having electrically floating body transistor

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Memory device having electrically floating body transistor

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Memory cell comprising first and second transistors and methods of operating

Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

MRAM access coordination systems and methods via pipeline in parallel

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Systems and methods for reducing standby power in floating body memory devices

A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Word line decoder memory architecture

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.

Circuit engine for managing memory meta-stability

Growing community of inventors

Fremont, CA, United States of America

Benjamin S Louie