Intel Corporation

Benjamin Pletcher

Yoav Harel

Carlos Nava Rodriguez

Steven Spangler

Joy Chandra

Prosun Chatterjee

Abhishek R Appu

Joydeep Ray

Michael Apodaca

Larry D Seiler

Hema Chand Nalluri

Vamsee Vardhan Chivukula

Sudarshanram Shetty

Rahul Kumar

Aditi Gautam

Jonathan Hersh

Bret Martin

Embodiments described herein are generally directed facilitating out-of-order execution of GPU texture sampler operations. An embodiment of a method includes a texture sampler of a GPU maintaining (i) a latency queue operable to store information regarding a set of transactions associated with each of multiple texture sampler operations and (ii) multiple virtual channel (VC) queues each operable to store information regarding transactions for a respective single texture sampler operation at a time. Out-of-order processing of the texture sampler operations is facilitated by making use of the latency queue and the VC queues. For example, during a transaction processing interval, the availability of data in a cache for the transactions associated with each of the VC queues may be determined. A VC queue may be selected based on the determined availability of data. A transaction associated with a head of the selected VC queue may then be processed.

Out-of-order execution of graphics processing unit texture sampler operations

Embodiments described herein are generally directed to a local cache structure within a shared function of a 3D pipeline that facilitates efficient caching of resource state. In an example, the cache structure is maintained within a sub-core of a GPU. The local cache structure includes (i) an SC having entries each containing a state of a binded resource, and (ii) a DSAT having entries each containing an index into the SC. The DSAT is tagged by SBTO values representing addresses of entries of a binding table. A request, including information indicative of an SBTO pointing to an entry within the binding table, is received for a state of a particular binded resource being accessed by a shared function of the 3D pipeline. Based on the SBTO and during a single access to the cache structure, a determination is made regarding whether the state of the particular binded resource is present.

Efficient caching of resource state for a shared function of a three-dimensional pipeline of a graphics processing unit

Dynamic routing of texture-load in graphics processing is described. An example of a processor includes one or more processing resources, the one or more processing resources to load a message including a texture load; a texture sampler and a data port; and a message router to route the texture load to a destination, wherein the destination may be either the texture sampler or the data port; wherein the message router includes arbitration circuitry to select the destination for the texture load, the arbitration circuitry to base selection of the destination at least in part on support by the data port for a format of a memory surface for the texture load; and a utilization metric for the data port representing availability of the data port.

Dynamic routing of texture loads in graphics processing

Methods and apparatus relating to conversion of an unsigned normalized (unorm) integer values to floating-point (float) values in low power are described. In an embodiment, conversion logic converts a unorm integer value to a floating-point value based on detection of whether the unorm integer matches one of three cases, wherein the unorm integer value comprises n bits. Memory stores a count value corresponding to n&#x2212;1 bits of the unorm integer value after detection of a leading 1 in the unorm integer value. The three cases include: a first case with all zeros, a second case with all ones, and a third case with a combination of one or more zeros and one or more ones. Other embodiments are also disclosed and claimed.

Conversion of unorm integer values to floating-point values in low power

A method, graphics processing unit, and system are described herein. The method for adaptive anisotropic filtering includes calculating a number of ways of anisotropy based on a computed level of detail of a texture map and applying a bilinear low pass filter to a texture map's closest two MIP maps using a processor. An effective number of ways and filter sizes may be computed on each of the closest two closest MIP maps. Additionally, the closest two MIP maps may be sampled at their respective effective number of ways. The method also includes applying a corresponding sized low pass filters to each of the closest two MIP maps, and combining the filtered closest two MIP maps using a weighted sum based on a fractional part of a computed level of detail.

Adaptive anisotropic filtering

Embodiments described herein include a graphics processing unit. The graphics processing unit includes a plurality of execution units. The graphics processing unit also includes a plurality of sampler units. Each sampler unit corresponds to a sampler dispatch logic unit and at least one execution unit, and the sampler dispatch logic units are used to network the plurality of sampler units.

Sampler load balancing

A reconfigurable floating point data filter may be implemented by configuring a texture filter in response to state data, where the state data specifying at least a data width of input texture data to be filtered, where the input texture data is in a floating point format, filtering the input texture data using the texture filter, and then reconfiguring the texture filter to be substantially fully utilized when the data width of the input texture data changes.

Growing community of inventors

Mather, CA, United States of America

Benjamin Pletcher