Texas Instruments Corporation

Benjamin P McKee

Shaofeng Yu

Frank Scott Johnson

Angelo Pinto

F Scott Johnson

Tad Grider

Thomas J Aton

James Walter Blatchford

Benjamen M Rathsack

Edmund David Burke

Carl Albert Vickery, Iii

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.

System and method for making photomasks

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming ()-oriented silicon regions for NMOS and () regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has () and ()-oriented regions. The method forms a directly bonded silicon (DSB) layer of ()-oriented silicon on a ()-oriented substrate. The DSB layer is removed in the NMOS regions and a ()-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.

Methods for transistor formation using selective gate implantation

A method for manufacturing an integrated circuithaving transistorsof two threshold voltages where protected transistor stackshave a gate protection layerthat are formed with the use of a single additional mask step. Also, an integrated circuithaving at least one polysilicon gate transistorand at least one FUSI metal gate transistor

Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors

Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

Methods for transistors formation using selective gate implantation

A capacitive structure (). The capacitive structure comprises a semiconductor base region () having an upper surface, a well () formed within the semiconductor base region and adjacent the upper surface, a first dielectric layer () adjacent at least a portion of the upper surface, and a polysilicon layer () adjacent the first dielectric layer. The well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension. The capacitive structure further comprises a first conductive layer () positioned with at least a portion overlying at least a portion of the polysilicon layer, a second dielectric layer () adjacent the first conductive layer, and a second conductive layer () adjacent the second dielectric layer. The first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension.

High capacitive density stacked decoupling capacitor structure

Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.

Growing community of inventors

Richardson, TX, United States of America

Benjamin P McKee