Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies Enterprise IP (singapore) Pte. Ltd.

Benjamin P Haugestuen

David Lawrence Linam

Richard S Rodgers

Scott T Evans

Howard L Porter

A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design.

Systems, methods, and programs for leakage power and timing optimization in integrated circuit designs

An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.

Interfaces, circuits, and methods for communicating with a double data rate memory device

A method and apparatus is presented for debugging and testing a memory controller. In one embodiment, a testing interface is presented for performing stuck-at testing. In a second embodiment, a testing interface is presented for observing clock timing in a memory controller.

System and method for testing and debugging analog circuits in a memory controller

A delay line architecture is presented. In one embodiment, the delay line is used to introduce delay compensation into a circuit design at the top level of the circuit design.

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Fort Collins, CO, United States of America

Benjamin P Haugestuen