Lsi Logic Corporation

Benjamin Mbouombouo

Weidan Li

Johann Leyrer

Juergen K Lahner

Human Boluki

Anwar Ali

Stefan Graef

Sudhakar Sabada

Bo Shen

Alexander Y Tetelbaum

Juergen Dirks

William Loh

Peter J Wright

Prasad Subbarao

Maad A Al-Dabagh

Radoslav Ratchkov

Max M Yeung

Thomas Mathews Antisseril

Ludger F Johanterwage

Hiroshi Ishikawa

Dana Ahrens

An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method

A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.

Method of optimizing critical path delay in an integrated circuit design

A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated circuit architecture that includes a plurality of modules and an internal I/O ring; (b) creating a floorplan to define an area for placing module cells for each module in the plurality of modules wherein for each module that overlaps the internal I/O ring, an area of intersection between the area defined for placing the module cells and an area bounded by a side of the internal I/O ring for which the area of intersection is least is a global minimum for the plurality of modules; and (c) generating as output the floorplan for the integrated circuit architecture.

Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ring

An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.

Optimized buffering for JTAG boundary scan nets

A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

Design methodology for dummy lines

A method and system is disclosed to improve the turnaround time to provide adequate time to meet project schedules in the event that adjustments or modifications to the design are necessary. A method for improving a turnaround time for design verification of a process database representing a semiconductor design includes the steps of (a) deriving a timing database and a (DNE) database from the process database; (b) performing, using the timing database, one or more design changes and one or more timing verifications and corrections to generate a modified timing database; (c) initiating, using the process database, physical validation of the semiconductor design prior to completion of step (b) to generate a modified DNE database; (d) merging the modified timing database with the modified DNE database to form a modified process database; and (e) performing, using the modified process database, one or more design verification checks of the semiconductor design.

Split and merge design flow concept for fast turnaround time of circuit layout design

A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

Donut power mesh scheme for flip chip package

A computer readable medium encoded with instructions for executing the steps of: receiving information about a driving cell from a layout tool, receiving information about an interconnect from a layout tool, determining buffer cell information based upon information about the driving cell and the interconnect by accessing a previously defined library lookup table, relaying the buffer cell information from the library look up table to the layout tool.

Buffer cell insertion and electronic design automation

A method and apparatus are provided for estimating gate leakage of an integrated circuit design having a plurality of transistors. The method and apparatus simulate an operating state of the integrated circuit design and estimate the gate leakage as a function of the states of the transistors in response to the simulated operating state.

Method and apparatus for estimating state-dependent gate leakage in an integrated circuit

A power distribution system for distributing external power across a die is disclosed, wherein the die has horizontal and vertical centerlines. The system and method include providing a power mesh that includes a plurality of V-shaped trunks patterned as concentric diagonal trunks extending from the horizontal and vertical centerlines of the die towards the periphery of the die.

Die power distribution system

An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.

Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells

An improved metal stack strategy is disclosed. A first aspect of the present invention provides a method for defining an optimized metal stack option based on critical path information. The method and system use interconnect data from timing critical paths from at least one previous design to generate interconnect statistical data. The interconnect statistical data is then used to vary physical properties of interconnects in a current design during simulation until optimum performance is achieved. A second aspect of the present invention provides a method for reusing an ASIC core design with different metal stack options. This method defines x common metal layers across at least two metal stack options, where interconnects on each of the metal layers have common physical and electrical characteristics. An ASIC core design based on the x common metal layers is also defined, thereby making the ASIC core compatible with the different metal stack options. Given custom ASIC designs, each having a total of y metal layers where y>x, respective custom ASICS may then be fabricated using the ASIC core design and different metal stack options.

Optimized metal stack strategy

A method for characterizing cell interconnect delay is disclosed that may be included in a library for use with logic design tools. A method of characterizing cell interconnect delay includes the steps of (a) receiving as inputs a plurality of input ramptimes and a plurality of interconnect lengths for a selected cell, and (b) calculating an output ramptime and a total cell delay including a cell delay and an interconnect delay for each of the plurality of input ramptimes for each of the plurality of interconnect lengths for the selected cell from the inputs.

Cell interconnect delay library for integrated circuit design

A method for performing timing driven interconnect estimation analysis is disclosed. The method includes collecting data only from timing critical paths of at least one previous design, and generating statistical data based on a net length distribution of the timing critical paths. A wire load model is then generated for a new design from the statistical data.

Timing driven interconnect analysis

A power distribution system for distributing external power across a die is disclosed, wherein the die has multiple sides, and a plurality of power bond pads located along each of the sides for receiving an external power signal. The system and method include patterning a plurality of straight power lines that form a single-layer power mesh diagonally across the die to connect the power bond pads that are located on two different sides of the die. As an alternative to the first embodiment, the diagonal power lines are patterned in a stair-step configuration for ease of manufacturing.

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San Jose, CA, United States of America

Benjamin Mbouombouo