Axis Semiconductor, Inc.

Axiowave Networks, Inc.

Benjamin Marshall

Xiaolin Wang

Qian Wu

Ke Ning

Gregory Steve Pitarys

Fugui Wang

Ajay C Mahagaokar

Satish Soman

Subhasis Pal

Stephen E Smith

Gregory Pitarys

Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Instruction set design, control and communication in programmable microprocessor cores and the like

The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions

A novel fault-tolerance technique for protecting against and correcting errors in packet data stream flow, preferably through not exclusively with closed ring sequential address generators and the like, through the use of pairs of independent but linked packet data flow paths enabling discarding of error data occurring in one path and substituting therefor corresponding correct data from the other path to enable continuation of the data stream flow without interruption and without error.

Method of and apparatus for correcting errors in data packet flow streams as in closed ring sequential address generators and the like without data flow stream interruption

A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.

Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor

Growing community of inventors

Stow, MA, United States of America

Benjamin Marshall