Iowa State University Research Foundation Inc

Benjamin Magstadt

Degang James Chen

Yuming Zhuang

The present disclosure relates to a digital-to-analog converter (DAC) linearization system including a DAC, a summing buffer structure, an analog-to-digital converter (ADC), a calculation system, an error look-up table, and an adder. A combination of the DAC, the summing buffer structure, and the ADC sequentially provide first and second ADC output signals, both of which include DAC integral nonlinearity (INL). The calculation system calculates the DAC INL based on the first and second ADC output signals, the error look-up table provides a correction signal mapping to the calculated DAC INL, and the adder provides a calibrated digital input signal to the DAC based on the correction signal. The calibrated digital input signal ensures the DAC to generate an updated output signal with less nonlinearity and improved purity.

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Lincoln, NE, United States of America

Benjamin Magstadt