Texas Instruments Corporation

Benjamin Lee Amey

John H Carpenter, Jr

Patrick Michael Teterud

Sigfredo Emanuel Gonzalez Diaz

Hung Nguyen

Wei Lu

Joseph A Devore

Timothy Patrick Pauletti

Vijayalakshmi Devarajan

Timothy Paul Duryea

Brett Jason Thompsen

Zhihong You

Kannan Soundarapandian

Teuta K Williams

Daijiro Otani

Taewoo Kwak

An example circuit includes a substrate including a first transistor of a gate driver output stage, the substrate including a first well region; a diode circuit including a first terminal and a second terminal, the first terminal coupled to a first tap of the first well region; and a second transistor including a first terminal, a second terminal, and a body, the first terminal of the second transistor coupled to a switching voltage terminal, and the second terminal and the body of the second transistor coupled to the first tap of the first well region and to the first terminal of the diode circuit.

Apparatus and methods to control well bias in a semiconductor device

A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.

High-side gate over-voltage stress testing

A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.

An apparatus is provided. In the apparatus, there is comprises a substrate with a first region of a first conductivity type, a second region of a second conductivity type that is substantially surrounded by the first region, and a third region of the second conductivity type that is substantially surrounded by the second region. A first dielectric layer is formed over the substrate, and a first conductive layer is formed over the first dielectric layer, which is configured to form a first electrode of a capacitor. A second dielectric layer is formed over the first conductive layer. A plate is formed over the second dielectric layer so as to form a second electrode of the capacitor. A cap is formed over the second dielectric layer, being spaced apart from the plate. A via is electrically coupled to the cap and the third region, extending through the first and second dielectric layers.

Overvoltage testing apparatus

An apparatus is provided. The apparatus comprises a reference circuit and a startup circuit. The reference circuit is adapted to provide a startup current, while the startup circuit receives the startup current and outputs an output voltage. The startup circuit includes a current mirror, a first NMOS transistor, a second NMOS transistor, diodes, and a third NMOS transistor, and a control circuit. The first and second NMOS transistors are coupled to the current mirror at their sources and are coupled to one another and to the reference circuit at their gates. The diodes are coupled between the gate of the second NMOS transistor and the source of the second NMOS transistor, and the third NMOS transistor is coupled to the source of the second NMOS transistor at its gate (which also provides the output voltage at its source). The control circuit is then coupled to the drains of the first and second NMOS transistors.

Reference circuit with reduced current startup

Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.

Circuits, devices and methods for regulator minimum load control

A thermal shutdown circuit for protecting a main FET that conducts a load current ILOAD. A reference circuit provides a temperature current proportional to temperature. A thermal sensor circuit has a resistor and generates an output signal signaling thermal shutdown when the voltage generated across the resistor by the temperature current exceeds a predetermined value. A sense FET having a size smaller than the main FET conducts a sense current ISENSE proportionately smaller than ILOAD. A current mirror mirrors a scaled current proportional to ISENSE to be conducted through the resistor, the scaled current being scaled so as to cause the voltage generated across the resistor to exceed the predetermined value when ILOAD exceeds a predetermined value.

Thermal shutdown trip point modification during current limit

A wake-up circuit for a ECU on a CAN bus utilizes two complementary switching transistors which will turn ON when there is a differential voltage between CANH and CANL which will turn ON the transistors to pass a current which will be mirrored over to create a voltage which will switch a comparator or a Schmitt trigger. The two signals are then ORed together to generate a digital wake-up signal that can be utilized by other on-chip circuitry.

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Allen, TX, United States of America

Benjamin Lee Amey