Apple Inc.

Google Inc.

Other

Nvidia Corporation

Benjamin K Dodge

Jason Rupert Redgrave

Manu Gulati

Xiaoyu Ma

Jaideep Dastidar

Harshavardhan Kaushikkar

Shawn Munetoshi Fukami

Vinodh R Cuppu

Yiu Chun Tse

Nachiappan Chidambaram Nachiappan

Peter F Holland

Albert Meixner

Gurjeet S Saund

Deniz Balkan

Keith Robert Pflederer

Allan Douglas Knies

Vinod Chamarty

Hongil Yoon

Rahul Jagdish Thakur

Weiping Liao

Ripudaman Singh

Yang Yang

Hao Chen

Brian P Lilly

Olivier Jean Benoit

James Vash

Srinivasa Rangan Sridharan

Per Hakan Hammarlund

Michael Bekerman

Munetoshi Fukami

Prasad Modali

Neeraj Parik

Wolfgang H Klingauf

Tony Yuhsiang Cheng

Rong Zhang Hu

Vinoth Kumar Deivasigamani

Howard Tsai

Hon Fei Chong

Christopher D Shuler

Hengsheng Geng

David L Trawick

Tsungyi Lin

Thejasvi M Vijayaraj

If a secure element accesses a resource that is separate from the secure element, conducting a secure transaction can be inefficient in terms of power or time. Power usage is inefficient if the resource is never permitted to sleep, and transaction time is inefficient if the resource is permitted to sleep, and the user experiences a delay. To enable dual efficiency, a resource entity is permitted to be powered down. The resource entity is then powered up speculatively by an activation controller. The activation controller predicts an upcoming secure transaction based on sensor output, such as a position fix or a detected electromagnetic field. Based on monitored sensor output, the activation controller issues an activation signal to power up the secure element or the resource entity prior to initiation of the upcoming secure transaction. Thus, power can be conserved without introducing a transaction-processing latency.

Speculative activation for secure element usage

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.

Synchronized data chaining using on-chip cache

A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

Systems and methods for arbitrating traffic in a bus

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

Way partitioning for a system-level cache

A rope clasp device for securing a rope eliminates the need for a knot in a rope by selectively clasping and encasing at least one portion of a rope in a toothed clamp. The rope clasp device comprises a base, at least one, but generally two swinging doors, and a lock. The swinging doors are pivotably coupled to the base in order to be moved between an open position and a closed position. In the closed position, a pair of channels for passage of a rope is defined between the base and the doors. The channels are defined by a plurality of clasping teeth to retain the rope therein.

Rope clasp

A system and method for efficiently allocating data storage to agents. A computing system includes an interconnect with intermediate buffers for storing transactions and corresponding payload data during transport between sources and destinations. A data storage limit is set on an amount of data storage corresponding to outstanding transactions for each of the multiple sources based on the initial buffer assignments. A number of outstanding transactions for each of the multiple sources is limited based on a corresponding data storage limit. If the rate of allocation of a given buffer assigned to a first source exceeds a threshold, then a second source is selected with available space exceeding a threshold in an assigned buffer. If it is determined the second source is not assigned to a buffer with a rate of allocation exceeding a threshold, then buffer storage is reassigned from the second source to the first source.

Systems and methods for providing a back pressure free interconnect

Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

Method and apparatus for ensuring real-time snoop latency

In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

Communication queue management system

Systems, apparatuses, and methods for time shifting tasks in a computing system. A system may include a display control unit configured to process pixels for display. The display control unit may include at least one or more pixel processing pipelines, a control unit, and a pixel buffer. The control unit may be configured to monitor the amount of data in the pixel buffer and set the priority of pixel fetch requests according to the amount of data in the pixel buffer. If the control unit determines that an inter frame period will occur within a given period of time, the control unit may prevent the priority of pixel fetch requests from being escalated if the amount of data in the pixel buffer falls below a threshold. The control unit may also be configured to fill the buffers of the display control unit with as much data as possible during the inter frame period.

Systems and methods for time shifting tasks

Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.

Credit lookahead mechanism

Growing community of inventors

San Jose, CA, United States of America

Benjamin K Dodge