Agere Systems Inc.

Alcatel-Lucent USA Inc.

Canon Kabushiki Kaisha

Lucent Technologies Inc.

Benjamin John Widdup

Mark Andrew Bickerstaff

Graeme Woodward

Koen Van Den Beld

Graeme Edwin Pope

Mark Patrick Barry

A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity.

Modified branch metric calculator to reduce interleaver memory and improve performance in a fixed-point turbo decoder

A method and system for improving buffer compression in automatic retransmission request (ARQ) systems includes both a compander and decompander for further processing data. A received data string k bits in length is first companded according to a predetermined companding scheme. The companded data string is reduced to a length of k&#x2212;1 bits for more efficient storage. Upon receipt of a request for retransmission, the stored companded data string is loaded and decompanded back to a length of k bits. Once decompanded, the data string is combined with a retransmitted data string to produce a single data string with an increased likelihood of being correct. By companding the data string before storage, a smaller memory block can be used for the storage of the data string.

Buffer compression in automatic retransmission request (ARQ) systems

Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of the plurality of sub-matrices has a single entry. Each of the sub-matrices has at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, wherein one or more of the memory elements may be selectively disabled. The Phi-nodes may be selectively disabled, for example, at run-time. The Phi-node optionally further comprises a multiplexer in order to provide a variable parity check matrix.

Method and apparatus for block and rate independent decoding of LDPC codes

An interleaver parameter generator circuit used to calculate and generate on an as needed basis interleaver parameters for interleaving blocks of information of varying lengths in accordance with a pseudorandom pattern defined by the 3GPP standard. The interleaver parameter generator circuit calculates and generates the defined interleaver parameters based on an input parameter that represents the length of the block of information to be interleaved. At least one of the defined parameters is calculated and generated using a decomposed form of its definition. The interleaver parameter generator circuit uses well known circuit blocks such as multipliers, subtractors, Compare-and-Select circuits and other circuits to calculate and generate the defined parameters.

Parameter generation for interleavers

In a decoder, the BER is calculated during a decode operation of the decoder. Access to decoder components for obtaining signal data for use in calculating the BER is provided during the decode operation when the components are not used by the decoder. A fetch component serves to provide the input signal to both the decoder and BER calculator at the same time. The BER calculator calculates the BER based on the output from the previous iteration. Since the decoder keep decoding the data until the final two iterations result in the same output, the calculation of the BER can be performed during the last iteration of the decoding process. An HDA early termination signal is used to confirm an accurate BER calculation.

BER calculation device for calculating the BER during the decoding of an input signal

An architecture for a turbo decoder performs a faster max* computation. In this architecture, one or more lookup tables begin processing a digital signal prior to the most significant bit of the digital signal stabilizes. This technique allows processing in the lookup table to be accomplished during a period of time in which processing could not be accomplished previously. As a result, the architecture performs the max* computations at a faster rate than previous architectures.

Architecture for a faster max* computation

A memory controller ( ) is disclosed which includes a write arbiter ( ) and a read arbiter ( ) for receiving and processing memory requests from a number of requestor modules ( ) for accessing a high speed memory device ( ). A high speed controller ( ) controls data flow to and from the high speed memory device ( ) at a frequency that is higher than ail operating of the arbiters ( ), allowing pseudo-simultaneous memory transactions. A read data dispatcher ( ) is also disclosed for receiving data from the high speed controller ( ) in response to read transactions and for passing the data to one of the requestor modules ( ). The size and destination information for launched read transactions are kept by a queue . When return data is received by the read data dispatcher ( ), the read data dispatcher ( ) matches the appropriate amount of data with each queue entry and delivers that return data to the appropriate requester module ( ).

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Glenwood, Australia

Benjamin John Widdup