Intel Corporation

Benjamin Jann

Ashoke Ravi

Satwik Patnaik

William J Lambert

Sidharth Dalmia

Trang Thuy Thai

Jonathan Jensen

Ozgur Inac

Ofir Degani

Alexandros Margomenos

Hasnain Lakdawala

Elan Banin

Igal Kushnir

Ali Azam

Wayne Ballantyne

Gregory Chance

Bruce Geren

Sanket Jain

A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.

Methods and devices for selecting a desired sub-harmonic of a high-frequency clock

A wireless communication device can include an oscillator circuit. The oscillator circuit can include an oscillator and measurement circuitry coupled to the oscillator. The measurement circuitry can receive an output signal of the oscillator and measure oscillator error by comparing the output signal of the oscillator to a nominal frequency for an amount of time. The oscillator circuit can further include adjustment circuitry to adjust an oscillator frequency of the oscillator based on the measured oscillator error.

Opportunistic calibration of a clock

A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.

Interleaved sub-sampling phased array receiver

Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.

Antenna modules and communication devices

A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

Methods and devices for digital clock multiplication of a clock to generate a high frequency output

Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Local oscillator (LO) generation for carrier aggregation in phased array front ends

Injection-locked clock-multiplication for mixer local oscillator (LO) generation

Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.

Radio design, control, and architecture

Digital radio head control

A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.

Circuit and a method for operating a circuit

The disclosure is directed to a circuit arrangement and method that provide efficient concurrent transmit and receive, transmit only and receive only of wireless signals. In one implementation, a circuit arrangement is provided that incorporates uses a single antenna to achieve concurrent transmit and receive, transmit only and receive only of wireless signals. A dual amplifier structure may be provided, and at least one of the amplifiers associated with the dual amplifier structure is amplitude tunable in order to ensure that each amplifier of the dual amplifier structure provides substantially the same or the same signal amplification. Unwanted transmit signals detected by a receiving circuit arrangement may be used to cause a processor to generate a digital code word that is used to modify a signal amplification provided by at least one of the amplifiers associated with the dual amplifier structure.

Growing community of inventors

Hillsboro, OR, United States of America

Benjamin Jann