Maxim Integrated Products, Inc.

Tektronix, Inc.

Benjamin J McCarroll

Steven K Sullivan

Yusuf Haque

Brent R Jensen

Yaohua Yang

Chowdhury F Rahim

David W Entrikin

Kevin Kennedy Johnstone

Scott Lindsey Williams

Rie Sasakawa

An electronic device comprising a matched filter to drive a LED module is disclosed. The matched filter receives an incoming rectangular pulse and outputs a modulated driving signal to drive the LED module. The optical output from the LED is captured by an optical sensor and converted to electrical signal for analysis. A decimation filter couples to the optical sensor in an effort of reducing sampling rate and quantization noise of the converted electrical signal. The modulated driving signal output from the matched filter keeps the LED current, thus LED light, matching the time-mirrored impulse response of the decimation filter to obtain or approach a theoretical maximum signal-to-noise (SNR) at a fixed amount of power.

Matched filter techniques configured to fire led using a sloped response

The present invention is related to digital to analog converter (DAC) input data encryption off-chip and decryption on-chip to suppress input data in-band harmonic leakage through package related parasitic capacitance. More specifically, the present invention relates to the method and apparatus of input data encryption off-chip by forming the logical exclusive-OR of the raw data and a random single bit data stream. The encrypted data is then read onto the DAC chip where the data is decrypted using identical circuitry and an identical random single bit data stream. The off-chip encryption isolates harmonic content within the input data, preventing leakage of input data harmonic content through IC package-related parasitic capacitance into DAC outputs. Any leakage appears as an increase in spectral noise rather than output distortion and as such, has a much smaller impact on DAC narrow band linearity.

Data encryption for suppression of data-related in-band harmonics in digital to analog converters

The present invention is a technique for dynamic element matching used in digital-to-analog converters (DAC's). An analog-to-digital converter (ADC) converts an analog signal into a digital code. A current-mode randomizer randomizes the digital code based on a control word provided by a pseudo random number generator. A digital-to-analog converter (DAC) converts the randomized digital code into an analog signal.

Dynamic element matching using current-mode butterfly randomization

The present invention discloses a method and apparatus for correcting errors in N digital word generated by N&plus;1 pipelined analog-to-digital converters. The method comprises the steps of: (1) synchronizing the N digital words by N groups of pipeline registers; and (2) correcting the synchronized N digital words by performing either an incrementing operation or a decrementing operation based on an adjustment value.

Efficient error correction in pipelined analog-to-digital converters

A method of digital calibration for analog-to-digital converters providing implicit gain proration. In accordance with the method, the calibration begins at the center of the transfer curve rather from one end or the other. By beginning in the center, calibrating in the positive direction and then calibrating in the negative direction, the interstage gain errors are also corrected without an extra gain-proration cycle. In addition, the number of accumulated measurements is reduced by a factor of two for the final correction coefficient by using the preferred method. Therefore, the roundoff errors are also reduced.

Digital calibration for analog-to-digital converters with implicit gain

A phase detector biased in a manner to alleviate the mismatch between the biasing current sources and the phase detector core bias currents. The bias setting resistors are coupled together at a common node that forms the negative input of a differential feedback amplifier. The positive input to the amplifier is referenced to a reference voltage, and the output of the amplifier controls the biasing current sources. The feedback amplifier forces the average voltage at the current source outputs to approximately match the reference voltage applied to its positive input. Thus the average bias current from the bias current sources is forced to track the average bias currents of the phase detector core.

Phase detector

A current source includes a control stage responsive to a stable, d.c. input voltage that is operative to produce a control voltage proportional to absolute temperature (PTAT), and an output stage responsive to the PTAT control voltage that is operative to produce an output current that is an essentially constant fraction of an output constant current source. The control stage includes a temperature-dependent control resistor of a given resistor type, and at least one control constant current source providing the control resistor with a temperature dependent control current. The temperature dependent current source includes a temperature dependent current source resistor based on the given resistor type such that the temperature dependencies of the control current and the control resistor tend to cancel in such a manner that a true PTAT control voltage is developed. The output stage includes an output transistor coupled to an output constant current source such that an output current of the output stage has no current contribution other than from the output current source. A method for providing a current that is a constant fraction of an output constant current source includes the steps of: (a) developing a control current that is based on the same resistor type as a control resistor; (b) applying the control current to the control resistor to develop a control voltage that is proportional to absolute temperature; and (c) applying the control voltage to a current divider coupled to an output constant source to provide an output current.

Temperature stabilized constant fraction voltage controlled current

A high speed analog signal sampling system. The system comprises a timing chain having a plurality of delay elements arranged in series and a sample rate multiplier having a delay lock control system responsive to the outputs of first, second and third parallel delay elements in the sample rate multiplier to control the delay of the second parallel delay element so that its strobe signal output occurs one-half the time between the strobe signal outputs of the first parallel delay element and the third parallel delay element. The first, second and third parallel delay elements are the first three parallel delay elements of the timing chain, and a control signal of the delay lock control system is used to adjust and control the amount of delay introduced by every other parallel delay element after the second parallel delay element. The second and third parallel delay elements straddle one of the series delay elements in the timing chain, while the first parallel delay element has the same input as the second parallel delay element. The delay lock control system employs a sampling circuit which samples the strobe signal output of the first parallel delay element in response to an output of the second parallel delay element and which samples the strobe signal output of the second parallel delay element in response to an output of the third delay element, and further employs a control circuit which filters the difference between those two sampled output signals and provides that filtered difference as the control signal.

High speed analog signal sampling system

A fully differential CMOS peak detection circuit has a differential input stage and a negative feedback loop that form a differential unity gain feedback amplifier. The differential output of the differential input stage is applied to a differential peak detect circuit having a pair of series diode/capacitor combinations. The diode/capacitor junctions are applied to differential inputs of the negative feedback loop. A common mode correction circuit is coupled to the differential CMOS peak detection circuit to minimize differences between the common mode voltages of the differential input stage and the negative feedback loop. The differential peak voltage is held at the differential output of the differential input stage for sampling by a sampling circuit during a readback interval, and then tracks a differential input signal applied to the differential input of the differential input stage during a tracking interval. The differential peak detection circuit then peak detects during a peak detect interval that is equal to a desired sample time window.

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Portland, OR, United States of America

Benjamin J McCarroll