Nortel Networks Corporation

Cabletron Systems, Inc.

Teknovus, Inc.

Digital Equipment Corporation, Pat. Law Group

Benjamin J Brown

Ryan E Hirth

Glen Kramer

Lowell David Lamb

Richard P Modelski

Stephen D Augusta

Walter K Niskala

Michel W Carrafiello

James E Burgess

John P Roy

One embodiment of the present invention provides a system for mitigating Raman crosstalk between downstream data and video transmission in an Ethernet passive optical network (EPON), wherein the EPON includes an optical line terminal (OLT) and one or more optical network units (ONU's). During operation, the system transmits a data stream from the OLT to the ONU's on a first wavelength that is substantially at 1490 nm. The system also transmits a video signal stream from the OLT to the ONU's on a second wavelength that is substantially at 1550 nm. The system modifies the bit sequence for the data stream to change the power spectral distribution (PSD) for the data stream, thereby reducing power spectral content in the frequency range where significant Raman crosstalk can occur between data and video signal streams.

Method and system for mitigating Raman crosstalk in an Ethernet passive optical network

A high speed access bus interface for a communications network. The interface allows uni-directional transfer of data packets at a fast path processing rate of about 10 gigabits per second. The interface uses a master port and a slave port in a chip to chip data transfer scheme. The master and slave ports may have one or more than one data channel for transferring data packets. The master port includes a clock signal for synchronizing the transfer from the master port to the slave port. The slave may send an asynchronous signal to the master port in order to initiate the master port to stop or stall the pipeline transfer of data packets until space is made available in the slave port buffer. In addition to the clock synchronization, the interface utilizes an enable signal, a start of packet signal, an end of packet signal, an error signal (if necessary), a last valid byte signal, and a parity bit signal to identify, address, each data packet in the data stream. If a processing error occurs, the master port error signal to the slave port also initiates the slave port to disregard the previous data packet. The operating frequency of 50 MHz allows the data packet transfer to exceed 10 gigabits per second.

High speed access bus interface and protocol

A data buffering storage circuit automatically allocates a portion of shared storage area to the direction in which data buffering is required. This scheme allows use of fewer parts on a piece of networking hardware, which in turn lowers the cost, simplifies the design, and uses existing on-board memory in a more efficient manner. In at least one embodiment, a first area is allocated to the buffering of a first port of a network switch, a second memory area is allocated to the buffering of a second port of the network switch, and a third area is shared among the buffering of the first port and the buffering of the second port.

Method and apparatus for adaptive port buffering

A technique for managing bidirectional data flow between a first data bus, such as in a local area network, having a fixed data flow rate once access has been obtained, and a memory or storage device connected to a second data bus having variable latency. Inbound data from the first data bus are temporarily stored in a receive buffer memory and later forwarded to the storage device. Outbound data bursts are retrieved from the same storage device, temporarily stored in a transmit buffer memory, and later transmitted onto the first data bus. The invention controls the steps of forwarding inbound data to the storage device and retrieving outbound data from the storage device, in such a manner as to make efficient use of the second data bus and to minimize the possibility of overflowing the receive buffer memory during a receive operation, or underflowing the transmit buffer memory during a transmit operation. When transmitting is in progress, priority is given to supplying outbound data to the transmit buffer memory, with any inbound data being processed only if the transmit buffer memory is sufficiently full. When receiving is in progress, priority is given to emptying inbound data from the receive buffer memory, with any outbound data being processed only if the receive buffer memory is sufficiently empty. When neither transmitting nor receiving is in progress, priority is giving to emptying the receive buffer memory, then filling the transmit buffer memory.

System for minimizing underflowing transmit buffer and overflowing

Growing community of inventors

Chichester, NH, United States of America

Benjamin J Brown