Imec Vzw

Vrije Universiteit Brussel

Benjamin Hershberg

Jan Craninckx

Ewout Martens

Nereo Markulic

Barend Wilhelmus Marinus Van Liempd

Jorge Luis Lagos Benites

Barend Van Liempd

Nathalie Fievet

A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

Device and method for enhancing voltage regulation performance

An apparatus is provided for on-chip reconstruction of transient settling behavior. The apparatus comprises a first sampling circuit configured to sample a tracked analog signal output from a circuit under test over an operating period at a first sampling time, thereby generating a first sample output. In addition, the apparatus comprises a second sampling circuit configured to sample the tracked analog signal output at a second sampling time, thereby generating a second sample output. The apparatus further comprises a signal subtraction circuit configured to perform subtraction of the first sample output and the second sample output, thereby generating a difference signal. Moreover, the apparatus comprises a signal conversion circuit configured to output the difference signal in the digital domain.

Apparatus and method for on-chip reconstruction of transient settling behavior

A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.

Multiplying digital-to-analog conversion circuit

The disclosed technology relates to a method for improving performance of a feedback circuit comprising an amplifier and a feedback network, wherein the feedback circuit has at least one tunable component. In one aspect, the method comprises measuring first amplitude values at an input of the amplifier and second amplitude values at an output of the amplifier, estimating a linear open-loop gain of the amplifier based on both the amplitude values, estimating a linear finite gain error based on the estimated gain and the second amplitude values, subtracting the linear finite gain error from the first amplitude values to derive a set of samples containing second error information, deriving an signal-to-noise-plus-distortion ratio estimate based on the variance of the set of samples and a variance of the second amplitude values, and adjusting the feedback circuit in accordance with the signal-to-noise-plus-distortion ratio estimate.

Method for improving feedback circuit performance

A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.

Analog-to-digital converters

A system having a tunable impedance network and a method of tuning a tunable impedance network are disclosed. In one aspect, a telecommunications device comprises an electrical-balance duplexer (EBD) circuit coupled to at least one output node of a transmit path (TXin), an antenna, and at least one input node of a receive path (RXout), wherein the EBD circuit is configured to isolate the transmit path from the receive path by signal cancellation, and a balancing network (Zbal) as part of the EBD circuit. In one embodiment, the balancing network is an integrated tunable impedance network configured to provide an impedance that matches a target impedance (Zant) associated with the antenna at a first frequency and simultaneously at a second, different frequency. The network comprises a first portion and a second portion, the first portion reducing the influence of the tuning of the second portion at the first frequency. In some embodiments, the network preferably comprises no explicit resistors.

Telecommunications device comprising an EBD circuit, a tunable impedance network and a method for tuning a tunable impedance network

The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.

Input circuit for a dynamic comparator

A tunable impedance network includes at least one variable impedance bank comprising a plurality of digitally controlled unit cells each connected from at least a first end to a routing wire. The tunable impedance network is provided with selection means arranged for selecting, based on a desired impedance, a corresponding predetermined digital control signal to be supplied to the variable impedance bank to switch-on a corresponding combination of the unit cells. Between each pair of unit cells in the variable impedance bank, a routing wire section is provided having a respective routing impedance. Each of the predetermined digital control signals is provided for switching-on a combination of unit cells in such a way that the routing impedance of the routing wire section is exploited to fine-tune the actual impedance generated by the variable impedance bank.

Integrated tunable impedance network

The present disclosure relates to a telecommunications device. The telecommunications device includes an electrical balance duplexer connected to an output node of a transmission path, an input node of a receive path, an antenna, and a tunable impedance. The electrical balance duplexer is configured to isolate the transmission path from the receive path by tuning the tunable impedance. The telecommunications device also includes a tuning circuit for tuning the tunable impedance. The tuning circuit includes amplitude detectors for measuring voltage amplitudes, phase detectors for measuring voltage phase differences, an impedance sensor for measuring an input impedance of the electrical balance duplexer, and a processing unit operatively connected to the detectors, the impedance sensor, and the tunable impedance. The processing unit is configured to calculate an optimized impedance value. The processing unit is also configured to tune the tunable impedance towards the optimized impedance value.

Growing community of inventors

Leuven, Belgium

Benjamin Hershberg