International Business Machines Corporation

Globalfoundries Inc.

Benjamin Herrenschmidt

Bradly George Frey

Paul Mackerras

Michael K Gschwind

Derek E Williams

Anthony J Bybell

Cathy May

Jon K Kriegel

Bartholomew Blaner

David A Larson Stanton

Hubertus Franke

Steven Mark Thurber

Jody B Joyner

Eric N Lais

Richard Loise Arndt

Jentje Leenstra

James Xenidis

Guerney D H Hunt

Andrew Matthew Theurer

Hung Qui Le

Maged M Michael

Naresh Nayar

Harold Wade Cain, Iii

Randal Craig Swanberg

Jose Eduardo Moreira

Richard Harold Boivie

William Eric Hall

Florian Alexander Auernhammer

Albert James Van Norstrand, Jr

Ronald Nick Kalla

Charles David Wait

Timothy Hume Heil

Andrew Henry Wottreng

Robert Dov Herzl

David A Campbell

Kenichi Tsuchiya

Jay Gerald Heaslip

John Martin Ludden

Jake Truelove

Priya Ashok Nagpurkar

Jason Michael Hopp

Maciej Piotr Tyrlik

Techniques of handling interrupt escalation are implemented in hardware. In at least one embodiment, an interrupt presentation controller (IPC) receives an event notification message requesting an interrupt, specifying an interrupt priority, and referencing a virtual processor (VP) thread. The IPC determines whether the VP thread matches any interruptible VP thread. If not, the IPC conditionally escalates the interrupt requested by the event notification message. Conditionally escalating the interrupt includes determining whether or not the interrupt priority is greater than the operating priority of any interruptible VP thread. If so, the IPC initiates escalation of the interrupt requested by the event notification message to a next higher software stack level by issuing an escalate message. If not, the IPC refrains from escalating the interrupt requested by the event notification message.

Techniques for handling escalation of interrupts in a data processing system

The present disclosure relates to a process-based virtualization system comprising a data processing unit. The system comprises a computer readable storage media, wherein a first memory component of the computer readable storage media is configured for access by an OS, secure and non-secure applications and the firmware, and wherein a second memory component of the computer readable storage media is configured for access by the firmware and not by the OS and the non-secure application. The data processing unit is configured to operate in a first mode of operation that executes a non-secure application process using the OS, and to operate in a second mode of operation that executes the secure application using the firmware, thereby executing application code using the second memory component.

Process-based virtualization system for executing a secure application process

A processor core processes a translation load instruction including a protection field specifying a desired access protection to be specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.

Translation load instruction with access protection

A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

Promotion of ERAT cache entries

A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.

Interruptible translation entry invalidation in a multithreaded data processing system

An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.

Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latency

Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.

Hardware based isolation for secure execution of virtual machines

In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Configurable I/O address translation data structure

Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

Transactional memory system supporting unbroken suspended execution

A technique for improving random number generation (RNG) security for a data processing system includes a storage subsystem of a processing unit receiving a first deliver a random number (DARN) operation. The storage subsystem issues the first DARN operation with a first value, retrieved from a first base address register (BAR), on a first bus. The processing unit receives (from a first RNG unit) at least one of a first data and a first indication (that indicate whether the first RNG unit is functional) when a second value stored in a second BAR of the first RNG unit is the same as the first value. In response to the first and second values not being the same or the first RNG unit not being functional, the storage subsystem issues the first DARN operation with the first value on a second bus that is coupled to a second RNG unit.

Random number generation security

Techniques for improving random number generation security

For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address. In response to the virtual address not matching at least one entry within a TLB comprising at least one entry stored for at least one previous translation of at least one previous address, the TLB controller translates the virtual address into a real page number using at least one page table and adding a new entry to the TLB with the virtual address and the real page number, wherein each at least one entry within the TLB identifies a separate privilege setting from among a plurality of privilege settings and a separate indicator of whether the address is within the shared address space.

Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces

In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space. In response to the TLB controller comparing the virtual address for the current context to a particular entry of at least one entry within the TLB comprising the at least one entry stored for a previous translation of a previous virtual address, the TLB controller only indicates a match between the process identifier field and a translation process identifier field within the particular entry of the TLB if the translation process identifier field is also set to the clamped value.

Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer

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Narrabundah, Australia

Benjamin Herrenschmidt