Atmel Corporation

Benjamin Francis Froemming

Emil Lambrache

Ian Fullerton

Morten Werner Lund

Yong Luo

Andrew K Au

Systems and methods for multi-protocol serial communication interfaces are described. One example system includes an interface module including a buffer for storing a protocol selection. The system includes a protocol module coupled to the interface module and configured for providing one or more serial communication protocols. Based on the protocol selection, one of the serial communication protocols is selected. The system also includes a serial engine module coupled to the interface module and the protocol module. The serial engine module is configured for transmitting and receiving data or commands based on the selected serial communication protocol.

Multi-protocol serial communication interface

Apparatus and methods for quickly switching active context between data pointer registers are disclosed. The apparatus can include a first register operable for storing a first data pointer and a second register operable for storing a second data pointer. A configuration register can provide a first signal specifying either the first or the second data pointer as an active data pointer. An instruction decoder can receive a data pointer instruction and output a second signal. The first and second signals can be independent from one another. Decoding logic coupled to the logic devices can output one of the first or second data pointers as the active data pointer in response to the first and second signals.

Switching data pointers based on context

A set of low-cost microcontroller extensions facilitates Digital Signal Processing (DSP) applications by incorporating a Multiply-Accumulate (MAC) unit in a Central Processing Unit (CPU) of the microcontroller which is responsive to the extensions.

Microcontroller with low-cost digital signal processing extensions

A stack pointer is copied to a stack pointer base to debug stack underflow. A move instruction, used to initialize the stack pointer, is modified to additionally copy the stack pointer to a stack pointer base register. During a course of execution in a single context, the stack pointer base sticks to the initial base value while the stack pointer is altered by a succession of PUSH and POP instructions. By monitoring for equivalence in the stack pointer and the stack pointer base values, a balanced number of PUSH and POP instructions is detected. If an equal number of PUSH and POP instructions is detected and an additional POP instruction is programmed, a stack underflow condition exists, an exception condition signaled, and exception flag produced. The exception condition allows the stack to be protected from an excessive POP instruction retrieving data out of context and subsequent loss of stack data.

Stack underflow debug with sticky base

Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response.

Fast read port for register file

The same microcontroller chip is configured to be either a Target version or a Link version of a microcontroller. The Target version runs an application program. To debug the Target microcontroller, the Link version of the microcontroller functions as a master debug microcontroller to the slave Target microcontroller running the application program. The Link microcontroller runs an interface translator program between a Host computer that runs a debug program, and the Target microcontroller. The Link microcontroller communicates with the Target microcontroller using a fast, 2-wire interface. The Link microcontroller communicates with the Host computer through a general purpose interface.

Dual CPU on-chip-debug low-gate-count architecture with real-time-data tracing

A serial peripheral interface apparatus has a second parallel write buffer to load in a subsequent data byte while a current data byte is being transferred serially through the apparatus instead of waiting for the previous data byte to complete the serial transfer and other commands to avoid write collision. The subsequent data byte is transferred into the second parallel write buffer only after the software driven CPU examines the status of a load enable and the status of a write buffer provided by a finite state machine controller. The software driven CPU orders the subsequent data byte to be transferred into the second parallel write buffer when the load enable is favorable and the second parallel write buffer is available. The load enable becomes favorable when a bit counter counts the first half of the transfer of the previous data set. Thus, the second parallel write buffer avoids the stretching the master clock and improves data throughput of the system.

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San Jose, CA, United States of America

Benjamin Francis Froemming