Raytheon Company

Telasic Communications, Inc.

Hughes Aircraft Company

Benjamin Felder

Lloyd Frederick Linder

Don C Devendorf

Erick M Hirata

William W Cheng

Howard S Nussbaum

William P Posey

Kelvin T Tran

Dwight D Birdsall

Wade J Stone

Roger N Kosaka

Kikuo Ichiroku

Hieu M Le

Donald G McMullin

Robert Tso

Louis F Linder

Michael F Clingempeel

William J Rinard

A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

Multi-mode analog to digital converter

A subranging analog to digital converter (ADC). The ADC () includes a novel resistive ladder () for a differential quantizer () and a novel summing node circuit (). The novel resistive ladder () includes an input terminal (), a plurality of serially connected resistors R coupled to the input terminal (), and a pair of complementary current sources (and) for maintaining a constant current flow through the ladder (). The novel summing node circuit () includes an input terminal () for receiving an input signal, a pair of complementary DACs (and) for generating a reconstruction signal, and a summing amplifier () for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC. The novel method () includes the steps of trimming the complementary current sources of the coarse quantizer to match each other (), trimming each of the DAC cells on one of the complementary DACs (), trimming the overall DAC gain to match the gain of the coarse quantizer (); and trimming the gain of the fine quantizer to match one coarse quantization Q level ().

Resistive ladder, summing node circuit, and trimming method for a subranging analog to digital converter

An RF transceiver with a low power chirp acquisition mode includes a pulse detection circuit, which initiates a low power chirp acquisition mode when an appropriate input pulse is received. While in chirp acquisition mode, all transceiver circuitry not required to determine the chirp rate is powered down, a low power fast-hopping LO generator is powered up to provide one or more LO signals to demodulate the incoming signal, and an active bandpass filter connected to filter the demodulated output is arranged to extend the width of its passband to include the chirp rate. The filtered signal is digitized with an ADC and processed to determine the incoming signal's chirp rate. The low power LO generator comprises a look-up table which provides a plurality of digital output word sequences, each of which represents a discrete LO frequency, to a sine-weighted DAC. The resulting varying frequency analog output signal is multiplied to produce the discrete LO signals needed to demodulate the input signal. Once the chirp rate is detected, the low power LO generator is powered down, the passband of the active bandpass filter is narrowed, and the remaining receiver circuitry is powered up to dechirp the RF input signal.

RF transceiver with low power chirp acquisition mode

A high performance ADC apparatus. The inventive apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution. The method for producing this result includes providing the baseline device having a selected dynamic range at a baseline clock rate; generating the baseline clock rate by translating a reference clock upward by a selected factor; decimating the data rate of the baseline device to a slower data rate so as to achieve a selected degree of oversampling; and producing an output data rate as a sub-multiple of the baseline clock rate with the selected output resolution at the slower data rate. The architecture includes a monolithic substrate on which the baseline ADC provides a dynamic range necessary to satisfy the performance requirements of the final ADC.

High resolution ADC based on an oversampled subranging ADC

A dither circuit is monolitically integrated with a subranging ADC to add a dither signal at the input of the ADC's fine quantizer element to randomize its nonlinear quantization level errors. Because the subranging ADC has at least one overlap bit, the amplitude of the dither signal can range up to at least 2.sup.M-1 LSBs of the fine quantizer without saturating it. The digital equivalent of the dither signal is subtracted at the output of the fine quantizer to maintain the ADC's overall SNR. The randomization of only the fine quantizer element avoids gaining up the nonlinear errors associated with the dither signal itself thereby improving the overall SNR. This approach optimizes performance for small input signals while sacrificing flexibility to correct other sources of error.

Monolithic circuit and method for adding a randomized dither signal to

A current steering circuit diverts bias current from a differential current summing amplifier's front end when the differential input exceeds a safe threshold level, thus preventing the amplifier's output stage from being overdriven. Diverting the front end's bias currents also turns off transistors within the amplifier's front end and thus protects the front end from damage which may otherwise result from excessive input signals.

Current feedback differential amplifier clamp

A diode bridge includes a plurality of diodes for coupling an input voltage signal to a holding capacitor for sampling when the diodes are forward biased, and uncoupling the voltage signal from the capacitor for holding when the diodes are reverse biased. The diode bridge has first and second bias current nodes. A constant current drain causes a constant bias current to flow out of the bridge. A transistor connects the first node to the drain for forward biasing the diodes, whereas a transistor connects the second node to the drain for reverse biasing the diodes. A bootstrap amplifier (A2) produces a variable control voltage which controls a pair of voltage-controlled constant current sources to cause the constant bias current to flow therethrough into the bridge. A transistor (Q7) couples the control voltage to the first current source for forward biasing the diodes, whereas a transistor couples the control voltage to the second current source for reverse biasing the diodes. The transistors are all bipolar and of the same conductivity type, preferably NPN.

Power-efficient sample and hold circuit using bipolar transistors of

A linear predictive ADC employs a fully feed forward design to extend its dynamic range, allow greater speed of operation, achieve stable operation and eliminate a requirement for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a subsequent value of the input signal. After conversion back to analog format, the predicted signal is compared with the actual subsequent value of the input signal to produce an error signal that is converted to a digital format by a second quantizer (Qf). The digital predicted signal is fed forward and combined with the digital error signal to produce a high precision digital output. The analog error signal is preferably amplified prior to digitation to take advantage of the full bit capacity of the second quanitzer (Qf), and then digitally de-amplified back to its original scale. Digital gain and offset adjustment mechanisms (44, 50) are preferably provided to compensate for amplification/de-amplification mismatches and system offsets. The quantizers (Qc, Qf), predictor (32) and a digital register (36) that interfaces between the predictor and the output combiner (46) are clocked in a set sequence to ensure that the predicted signal from the register (36) corresponds in time to the error signal presented to the output combiner (46).

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Saugus, CA, United States of America

Benjamin Felder