Nvidia Corporation

Benjamin Faulkner

Divya Ramakrishnan

Sreedhar Narayanaswamy

Swanand Santosh Bindoo

Mini Rawat

Tao Li

Jonah Matthew Alben

Tezaswi Raja

Rajeshwaran Selvanesan

Kevin Wilder

Aniket Naik

Amey Y Marathe

Fei (Walter) Li

Srinivasan Raghuraman

Peng Cheng Shen

Raj Jayakar

Tom Li

Daniel Rodriguez

Padmanabhan Kannan

A system to select graphics processing units (GPUs) to execute a task is disclosed. In at least one embodiment, GPUs are selected based on one or more task parameters and one or more fused parameters.

Static data center power balancing and configuration

Apparatuses, systems, and techniques to power balance multiple chips. In at least one embodiment, a system includes a plurality of processors having substantially equal performance capability and different power consumption capability, where a cumulative power consumption of the processors is not to exceed a system power threshold if each processor is operated at substantially peak performance.

Techniques to power balance multiple chips

Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.

Techniques to modify processor performance

A datacenter power management system and method is disclosed. A plurality of computing units are enabled to operate at a second frequency, higher than a first frequency, in response to determining from respective power coefficients for these computing units, that a power level at this higher frequency remains below a power budget.

Programmable power balancing in a datacenter

Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.

Techniques for configuring a processor to execute instructions efficiently

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San Jose, CA, United States of America

Benjamin Faulkner