Conexant Systems, Inc.

Benjamin Edwin Felta

Asif Shakeel

Stephen F Armen

The frequency of use of video and other data is increasing. Additionally, video components are typically connected together. The video components may synchronize via a first in first out (&ldquo;FIFO&rdquo;) queue. Data may be written into the FIFO queue by a component with a first clock rate, and then the data may be read out of the FIFO queue by a component with a second clock rate. Because of the different clock rates, it is possible that there could be an underflow or overflow of data in the FIFO queue. Typically, when the timing between the components is far apart, the read and write pointers that point into the FIFO queue are realigned by using a reset control signal, which sets both pointers back to address zero of the FIFO queue. The present system provides an improved technique for synchronizing the read and write pointers. In particular, the present system provides a technique for aligning the read and write pointers of a FIFO queue at any time and at any random address. This is especially useful to provide synchronization when a FIFO queue is used to pass data from a video system having a first clock rate to another video system having a different clock rate.

System for loading a saved write pointer into a read pointer of a storage at desired synchronization points within a horizontal video line for synchronizing data

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Cardiff, CA, United States of America

Benjamin Edwin Felta