Intel Corporation

Benjamin Duong

Kristof Darmawikarta

Srinivas V Pietambaram

Tarek A Ibrahim

Darko Grujicic

Aleksandar Aleksov

Brandon C Marin

Hari Mahalingam

Rengarajan Shanmugam

Leonel R Arana

Jeremy D Ecton

Suddhasattwa Nad

Changhua Liu

Bai Nie

Marcel Arlan Wall

Sashi S Kandanur

Srinivas Venkata Ramanuja Pietambaram

Telesphor Kamgaing

Pooya Tadayon

Yonggang Li

Sai Vadlamani

Thomas L Sounart

Hiroki Tanaka

Xiaoying Guo

Hongxia Feng

Haobo Chen

Roy Dittler

Marcel A Wall

Whitney Bryks

Helme Castro De La Torre

Miranda Ngan

Helme A Castro De La Torre

Thomas I Sounart

Michael Garelick

Chandrasekharan Nair

Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.

Photonic interconnect and components in glass

Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

Glass substrates having transverse capacitors for use with semiconductor packages and related methods

Position controlled waveguides and methods of manufacturing the same are disclosed. An example apparatus includes a substrate with a channel that extends into a first surface of the substrate to a second surface of the substrate, wherein the second surface is recessed relative to the first surface; buffer material having a first index of refraction on the second surface of the substrate; and a waveguide on the buffer material, the waveguide having a second index of refraction that is higher than the first index of refraction.

Position controlled waveguides and methods of manufacturing the same

An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.

Glass interposer optical switching device and method

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Capacitors in through glass vias

Various embodiments disclosed relate to photonic assemblies. The present disclosure includes methods for packaging a photonic assembly, including attaching a bridge die to a glass substrate, attaching an electronic integrated circuit die to the glass substrate and the bridge die, attaching a photonic integrated circuit die to the glass substrate and the bridge die, bonding a coupling adapter to the glass substrate and in situ forming a waveguide in the coupling adapted, the waveguide aligning with the photonic integrated circuit die.

Die last and waveguide last architecture for silicon photonic packaging

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.

Microelectronic assemblies having integrated magnetic core inductors

An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate, a plurality of integrated circuit devices electrically attached to the package substrate, wherein each integrated circuit device of the plurality of integrated circuit devices includes an active surface and a backside surface, and wherein a first integrated circuit device and a second integrated circuit device of the plurality of integrated circuit devices includes radio frequency logic circuitry and a radio frequency antenna formed in or attached thereto, and a radio frequency waveguide on the backside surface of the first integrated circuit device and on the backside surface of the second integrated circuit device.

Radio frequency antennas and waveguides for communication between integrated circuit devices

An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

Electronic substrates having embedded inductors

Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.

Etch barrier for microelectronic packaging conductive structures

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Phoenix, AZ, United States of America

Benjamin Duong