International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Applied Materials, Inc.

Internatoinal Business Machines Corporation

Benjamin David Briggs

Lawrence Alfred Clevenger

Michael Rizzolo

Christopher J Penny

Bartlet H Deprospo

Huai Huang

Theodorus E Standaert

Chih-Chao Yang

Leigh Anne H Clevenger

Nicholas Anthony Lanzillo

Elbert Emin Huang

Cornelius Brown Peethala

Joe Lee

Takeshi Nogami

Hosadurga K Shobha

Aldis G Sipolins

Koichi Motoyama

Jonathan Hudson Connell, Ii

Nalini Kanta Ratha

David Lee Rath

Raghuveer Reddy Patlolla

Maryam Ashoori

Jessica M Dechene

Lan Yu

James H Stathis

Tyler Sherwood

Gangadhara Raja Muthinti

Raghav Sreenivasan

Brent A Anderson

Terry Allen Spooner

James John Kelly

Jay William Strane

Takashi Ando

Ruqiang Bao

Deepika Priyadarshini

Spyridon Skordas

Chao-Kun Hu

Gen Tsutsui

Justin A Canaperi

Son Van Nguyen

Yuk Lung Chan

Hsueh-Chung Chen

Donald Francis Canaperi

Roger Allan Quon

Nicole A Saulnier

Eileen Patricia Tedesco

Kyle Gilbertson

Devika Sil

Daniel F Hogerty

Christoper J Penny

Leigh Anne Hodges Clevenger

Chen Zhang

Alfred Grill

Christian Lavoie

Ekmini Anuja De Silva

Yann Mignot

Kisik Choi

Ashim Dutta

Thomas J Haigh, Jr

Huy Cao

Patrick D Watson

Iqbal Rashid Saraf

Zihao Yang

Prasad Bhosale

Joseph F Salfelder

Han You

Processing methods may be performed to form a pixel isolation structure on a semiconductor substrate. The method may include forming a pixel isolation bilayer on the semiconductor substrate. The pixel isolation bilayer may include a high-k layer overlying a stopping layer. The method may include forming a lithographic mask on a first region of the pixel isolation bilayer. The method may also include etching the pixel isolation bilayer external to the first region. The etching may reveal the semiconductor substrate. The etching may form the pixel isolation structure.

Structure and method of bi-layer pixel isolation in advanced LCOS back-plane

A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Structure and method to improve FAV RIE process margin and electromigration

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.

Method of CMP integration for improved optical uniformity in advanced LCOS back-plane

Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

Structure and method of advanced LCoS back-plane having highly reflective pixel via metallization

Processing methods may be performed to form a grounded mirror structure on a semiconductor substrate. The methods may include revealing a metal layer. The metal layer may underlie a spacer layer. The metal layer may be revealed by a dry etch process. The method may include forming a mirror layer overlying the spacer layer and the metal layer. The mirror layer may contact the metal layer. The method may also include forming an oxide inclusion overlying a portion of the mirror layer. The portion of the mirror layer may be external to the spacer layer.

Structure and method of mirror grounding in LCoS devices

One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Optimizating semiconductor binning by feed-forward process adjustment

A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Selective recessing to form a fully aligned via

A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.

Paint on micro chip touch screens

A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Forming high carbon content flowable dielectric film with low processing damage

An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

Electrical device having conductive lines with air gaps therebetween and interconnects without exclusion zones

Structure and method to improve FAV RIE process margin and Electromigration

A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Selective ILD deposition for fully aligned via with airgap

The present invention provides for a cognitive system using an autonomous vehicle includes a plurality of sensors configured to obtain the weather forecast for a pollution detectable area; a cognitive input to determine the pollution detectable area having highest sensitivity of pollution; a light detecting and ranging system configured to spatially probe pollution levels distributed in the pollution detectable area; an evaluation system to evaluate the probed pollution levels in the pollution detectable area; and a recommendation system for recommending an action to be taken based on evaluation system results of the probed pollution levels in the pollution detectable area, wherein the pollution levels are detected based light emitted by the light detecting and ranging system.

Cognitive system for localized LIDAR pollution detection using autonomous vehicles

An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

Self-forming barrier for use in air gap formation

Growing community of inventors

Waterford, NY, United States of America

Benjamin David Briggs