Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Hewlett-packard Company

Benjamin Daniel Osecky

Blaine Douglas Gaither

Robert J Brooks

Andrew Ray Wheeler

David Fisk

Kathryn A Evertson

Dale Calvin Morris

Darel N Emmot

Jerome C Huck

Gerald J Kaufman, Jr

Carey Huscroft

Stephen B Lyle

Douglas Vincent Larson

Judson Eugene Veazey

Verna Knapp

Aland B Adams

Richard Glen Fowles

Dennis D Georg

In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Reflective memory bridge for external computing nodes

Thinning operating systems can include monitoring a number of functionalities of an operating system, the number of functionalities of the operating system being provided by a number of computing components loaded thereon. Thinning operating systems can include automatically identifying an undesired functionality of the number of functionalities during runtime and removing from the operating system at least one of the number of computing components providing the undesired functionality as a result of the automatic identification to thin the OS.

Thinning operating systems

Provided is a method for uniquely masking addressing to the cache memory for each user, thereby reducing risk of a timing attack by one user on another user. The method comprises assigning a first mask value to the first user and a second mask value to the second user. The mask values are unique to one another. While executing a first instruction on behalf of the first user, the method comprises applying the first mask value to set selection bits in a memory address accessed by the first instruction. While executing a second instruction on behalf of the second user, the method comprises applying the second mask value to set selection bits in the memory address accessed by the second instruction. The result offers an additional level of security between users as well as reducing the occurrence of threads or processes contending for the same memory address.

Address masking between users

A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.

Method and system for enhancing computer processing performance

A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.

Systems and methods for pushing data

A method for detecting computational errors in a digital processor executing a program. The program is divided into a plurality of computation sections, and two functionally identical code segments, respectively comprising a primary segment and a secondary segment, are generated for one of the computation sections. The primary segment is executed, after which a temporal diversity timer is started. The secondary segment is then executed upon expiration of the timer. The respective results of execution of the primary segment and the secondary segment are compared after completion of execution of the secondary segment, and an error indication is provided if the respective results are not identical.

Variable delay instruction for implementation of temporal redundancy

A system comprises a plurality of cache agents, a computing entity coupled to the cache agents, and a programmable mask accessible to the computing entity. The programmable mask is indicative of, for at least one memory address, those cache agents that can receive a snoop request associated with a memory address. Based on the mask, the computing entity transmits snoop requests, associated with the memory address, to only those cache agents identified by the mask as cache agents that can receive a snoop request associated with the memory address.

Mask usable for snoop requests

A method for detecting computational errors in a digital processor executing a program. Initially, the program is divided into computation segments, and source code for at least one of the segments is compiled to generate two redundant code sections. Comparison code is generated for comparing results produced by execution of the two code sections. Each of the code sections is then executed in a different computational domain to generate respective results. The results of the computation are executed to alter further flow of the program only if the respective results are identical.

Fault-detecting computer system

A method of allocating memory operates to avoid overlapping hot spots in cache that can ordinarily cause cache thrashing. This method includes steps of determining a spacer size, reserving a spacer block of memory from a memory pool, and allocating memory at a location following the spacer block. In an alternative embodiment, the spacer size is determined randomly in a range of allowable spacer size. In other alternative embodiments, spacers are allocated based upon size of a previously allocated memory block.

Method and program product for avoiding cache congestion by offsetting addresses while allocating memory

A cache memory system can determine that an entry is stale if the entry has not been accessed or modified for a predetermined time. If an entry is stale, the entry may be preemptively evicted. The predetermined time is made dynamically variable. A computer system can adjust the time to optimize a measure of performance. In a specific example, evicted lines are temporarily stored in an eviction queue. The time is adjusted to be as short as possible without substantially increasing the number of lines that must be recalled from the eviction queue.

Computer performance improvement by adjusting a time used for preemptive eviction of cache entries

A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may be further improve performance by limiting the number of dirty entries in a cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-cache transfer when the number exceeds a predetermined threshold. For either system, the predetermined threshold may be dynamically varied to determine a value that optimizes performance.

Computer performance improvement by adjusting a count used for preemptive eviction of cache entries

A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may further improve performance by limiting the number of dirty entries in the cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-ache transfer when the number exceeds a predetermined threshold.

Limiting the number of dirty entries in a computer cache

A multiprocessor computer system continues operation after the failure of a cooling device coupled to a central processing unit (CPU). In accordance with the present invention, an impending failure of a cooling device is detected, and all user and operating system processes are moved from the affected CPU coupled to the failing cooling device to one or more other CPUs. The system state is then altered so that interrupts are no longer received and processed by the affected CPU, and all memory caches associated with the affected CPU are flushed back to main memory to ensure cache coherency. At this point, the CPU is either powered-down, or placed in a low-power mode that allows the CPU to operate without the cooling device, while the processes that were removed from the suspended CPU continue executing on other CPUs. After the cooling device has been replaced and is operating normally, the CPU can be powered back up, interrupts can be enabled, and the CPU can once again execute user and operating system processes.

Method and apparatus for providing continued operation of a multiprocessor computer system after detecting impairment of a processor cooling device

An obstruction is removed from a computer system cooling fan by manipulating fan rotation. When a fan obstruction is detected, the fan is stopped. If the obstruction is caused by an object that was drawn toward the fan intake, such as a sheet of paper, this operation may clear the obstruction. The fan may also be reversed to attempt to blow the obstruction clear of the fan. Thereafter, the fan is returned to normal operation and is monitored to determine whether the obstruction was removed. If the fan is still obstructed, these steps can be repeated. If the attempts to clear the obstruction are unsuccessful, then the computer system operator or management software can be signaled.

Growing community of inventors

Fort Collins, CO, United States of America

Benjamin Daniel Osecky