Applied Materials, Inc.

Varian Semiconductor Equipment Associates, Inc.

Globalfoundries Singapore Pte. Ltd.

National University of Singapore

Nanyang Technological University

Applied Materials Israel Limited

Benjamin Colombeau

Naomi Yoshida

Hans-Joachim Ludwig Gossmann

Shiyu Sun

Theresa Kramer Guarini

Myungsun Kim

Johanes F Swenberg

Steven C H Hung

Michael Patrick Chudzik

Matthias Bauer

Michael Anthony Stolfi

Andy Lo

Sung Won Jun

Patricia M Liu

Malcolm J Bevan

Francis Lionel Benistant

Errol Antonio C Sanchez

Abhishek Dube

Wolfgang R Aderhold

Yi-Chiau Huang

Christopher R Hatem

Sanjay S Natarajan

Bingxi Sun Wood

Nam Sung Kim

Sheng-Chin Kung

Sai Hooi Yeong

Byeong Chan Lee

Vanessa Pena

Nilay A Pradhan

Lap Chan

Wei Liu

Mei Sheng Zhou

Abhilash J Mayur

Liang Choo Hsia

Yun Ling Tan

Ashish Pal

Bangun Indajang

Naved Ahmed Siddiqui

Russell Chin Yee Teo

Phillip Stout

Dennis P Rodier

Debora Chyiu Hyia Poon

Srinivas Gandikota

Christopher Dennis Bencher

Alex See

Yixiong Yang

Suketu Arun Parikh

Costel Biloiu

Craig Richard Chaney

Neil J Bassom

Nicolas L Breil

Jingmei Liang

Martin Jay Seamons

Kin Leong Pey

Dror Shemesh

Jacqueline S Wrench

Naushad K Variam

Adam Brand

El Mehdi Bazizi

Kyu-Ha Shim

Lin Dong

Mandar Balasaheb Pandit

Klaus Petry

Stanislav S Todorov

Tushar Mandrekar

Alex K H See

Linlin Wang

Steven C Hung

Dimitri R Kioussis

Yong Yang

Kevin S Jones

Baonian Guo

Amir Wachs

Dexter Xueming Tan

Chee Mang Ng

Fareen Adeni Khaja

Kurt T Decker-Lucke

Thirumal Thanigaivelan

Eric Davey

Uri Lev

Kourosh Nafisi

Clark Kuang Kian Ong

Mehdi Saremi

Aaron Lind

Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Horizontal GAA nano-wire and nano-slab transistors

Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

Gate all around device with fully-depleted silicon-on-insulator

Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.

Formation of gate all around device

Provided are methods of depositing a film in high aspect ratio (AR) structures with small dimensions. The method provides flowable deposition for seamless gap-fill, film densification by low temperature inductively coupled plasma (ICP) treatment (<600° C.), optional film curing, and etch back to form a low-k dielectric film having a dielectric constant, k-value less than 3.

Integrated flowable low-k gap-fill and plasma treatment

A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

Void-free contact trench fill in gate-all-around FET architecture

A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

Doping techniques

A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-κ dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-κ dielectric layer.

Treatments to improve device performance

Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

Conformal oxidation for gate all around nanosheet I/O device

A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

Threshold voltage modulation for gate-all-around FET architecture

Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

Selective silicon etch for gate all around transistors

Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

Methods for GAA I/O formation by selective epi regrowth

Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Gate all around I/O engineering

Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

Stress incorporation in semiconductor devices

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Salem, MA, United States of America

Benjamin Colombeau