National Semiconductor Corporation

Benjamin Clyde Buchanan

Laurence Douglas Lewicki

Amit Rane

Yongseon Koh

Nicolas Nodenot

Richard R Rasmussen

David Rosselot

Circuitry for adaptive signal equalizing with coarse and fine boost controls by providing multiple serially coupled stages of parallel controllable DC and AC signal gains with coarse and fine gain controls provided across all stages.

Adaptive signal equalizer with segmented coarse and fine controls

Method and system for adaptive signal equalizing with alternating boost and amplitude controls. In accordance with one exemplary embodiment, data signal boost control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a higher frequency, while sliced data signal amplitude control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a lower frequency.

System and method for providing adaptively equalized data signal with alternately adjusted data signal boost and sliced data signal amplitude

System and method for adaptive signal equalizing in which overlapping data signal equalization paths provide cumulative data signal equalization to provide multiple equalized data signals having different available amounts of equalization. Signal slicing circuitry slices the equalized data signals to provide multiple sliced data signals, from which the sliced data signal selected as an output data signal is dependent upon the data rate of the incoming data signal.

System and method for adaptively equalizing data signals with higher and lower data rates

A multi-port Ethernet Physical (PHY) layer device includes multiplexed datapaths and control logic such that each transmit data connection for a port may be mapped to any combination of the transmit data connections for one of multiple Media Access Control (MAC) layers, and each received data connection for a port may independently be mapped to an combination of the receive data connections for one of the MAC layers and the transmit data connection(s) for the other port(s). The device may be configured to operate in normal and port swap modes, to support failover switching and/or dedicated redundant connections, as a cable extender or media converter, as a snoop device, to form an Ethernet ring topology, for broadcast transmit or mirrored receive, or as a unidirectional repeater.

Independently configurable port redirection in a multi-port ethernet physical layer

A method for providing dynamic DC offset correction is provided. The method includes receiving a plurality of uncorrected samples. A determination is made regarding whether a specified number of consecutive uncorrected samples that correspond to a nominal voltage level has been received. When the specified number of consecutive uncorrected samples that correspond to the nominal voltage level has been received, an offset is generated based on an actual voltage level for each of the consecutive uncorrected samples.

Method and system for providing dynamic DC offset correction

An apparatus and method is disclosed for providing automated testing for an on-chip initialization counter circuit that comprises a plurality of counter flip-flop circuits that are used in the initialization of an integrated circuit. The apparatus comprises a state machine and a state machine counter circuit. The state machine receives signals from the initialization counter circuit and utilizes the signals to create a built-in self test output signal that indicates a current state within the initialization counter circuit. The state machine is capable of testing various operational states of an initialization counter circuit.

System and method for testing an on-chip initialization counter circuit

A method for clock deskewing using a continuously calibrated delay element in a phase-locked loop is provided that includes receiving a feedback signal. A skew select signal is received. The feedback signal is delayed based on the skew select signal to generate a delay output signal. The delay output signal is provided to a phase detector. An external clock signal and the delay output signal are received at the phase detector. A phase detector signal is generated based on the external clock signal and the delay output signal. A skewed clock signal and the feedback signal are generated based on the phase detector signal.

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Duluth, GA, United States of America

Benjamin Clyde Buchanan