Google Inc.

Advanced Micro Devices Corporation

Vmware, Inc.

Globalfoundries Inc.

Amazon Technologies, Inc.

Benjamin Charles Serebrin

Bhavesh Mehta

David A Kaplan

Eric Northup

Parthasarathy Ranganathan

Mark Douglas Hummel

Rama Krishna Govindaraju

Albert Borchers

Michael Roger Marty

Liqun Cheng

Timothy Jay Chen

Michael Haertel

Monish Shah

Bhavesh Davda

Richard Yoo

Grigory Makarevich

Paul Jack Turner

Kim Hazelwood

Kevin D Kissell

Jeffrey Clifford Mogul

Scott David Johnson

Rodney W Schmidt

Anton Chernoff

Daniel Michael Hecht

Jakov Seizovic

Keith Lowery

Yuhong Mao

Said Bshara

Brandon S Baker

Thomas R Woller

Patryk Kaminski

Raviprasad V Mummidi

Stephen David Glaser

Evgeny Schmeilin

Filippo Sironi

Elizabeth Morrow Cooper

Donald W McCauley

David James Goodell

Erich Boleyn

Joel Dylan Coburn

Daniel Hopper

Jonathan McCarrell McCune

Andrew Davenport

James Gabriel Watson

Robert Michael Kallal

Trevor Scott Bunker

John F Wiederhirn

Rolf Peter Neugebauer

Clinton Wills Smullen, Iv

Adrian Pearson

Ariana Meika Morgan

Rajeevardhan Gopalan

David Levinthal

Jonathan M Mccune

An input/output (I/O) device is coupled to a processor via a first peripheral bus and a second peripheral bus. The I/O device is configured to expose a first physical function (PF) and a second PF to a virtual machine (VM) executing on the processor. A first virtual function (VF) associated with the first PF is assigned to the first peripheral bus, and a second VF associated with the second PF is assigned to the second peripheral bus. The first VF and the second VF are exposed as a single VF to the VM. The VM can perform transactions with the I/O device via the single VF using the first peripheral bus and the second peripheral bus.

Bonding multiple peripheral ports to a single virtual machine

Described are techniques for write protecting a non-volatile memory (NVM) after the contents of the NVM have been set. In some examples, a computing device or system having an NVM also includes a Root of Trust (RoT) configured to generate a write protect command as an input to the NVM. The RoT generates the write protect command in response to detecting a write protect signal from an electronic controller. The write protect command sets one or more areas in the NVM to be read-only. Further, the write protect command can make the one or more areas read-only on a power-on basis so that write protection is maintained until the next power cycle. The electronic controller can be configured to assert the write protect signal each time the computing device or system is powered on, for instance during a reboot, thereby causing the RoT to renew the write protection.

Write protection using an immutable root of trust

Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one host's memory to another host's memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

System for live migration of virtual machines with assigned peripheral devices

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating signed addresses. One of the methods includes receiving, by a component from a device, a plurality of first requests, each first request for a physical address and including a virtual address, determining, by the component, a first physical address using the virtual address, generating a first signature for the first physical address, and providing, to the device, a response that includes the first signature, receiving, from the device, a plurality of second requests, each second request for access to a second physical address and including a second signature, determining, by the component for each of the plurality of second requests, whether the second physical address is valid using the second signature, and for each second request for which the second physical address is determined to be valid, servicing the corresponding second request.

Address validation using signatures

Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one hoses memory to another hoses memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Techniques for safe oversubscription of connection tracking entries are described. A method for safe oversubscription of connection tracking entries may include receiving a request for an allocation of a resource on a physical host in a provider network, the request received by a resource allocation monitor from an instance hosted by the physical host, determining a resource availability on the physical host, the resource availability based on a total amount of the resource on the physical host, a reserved amount of the resource to a plurality of instances hosted by the physical host, and a shared amount of the resource, and granting or denying the resource allocation based at least on the determined resource availability.

Safe oversubscription of connection tracking entries

In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2)-th of a memory page.

Increasing granularity of dirty bit information in hardware assisted memory management systems

Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising one or more processor cores, may determine that a process executing on a processing core causes one or more virtual memory pages to become disassociated with one or more previously associated physical memory addresses. The processing core which is executing that process which caused the disassociation may generate a TLB shootdown request. The processing core may transmit the TLB shootdown request to the other cores. The TLB shootdown request may include identification information, a shootdown address indicating the disassociated virtual memory page or pages which need to be flushed from the respective TLBs of the other cores, and a notification address indicating where the other cores may acknowledge completion of the TLB shootdown request.

TLB shootdowns for low overhead

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.

Data caching

IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.

Two stage command buffers to overlap IOMMU map and second tier memory reads

The present disclosure relates to managing an instruction cache based on temporal locality of cached instructions. One example method includes receiving a request for a first instruction included in a software application; storing the first instruction in a cache structure; receiving a request for a second instruction included in the software application; determining that a cache entry must be removed from the cache structure to create space to store the second instruction; determining that the first instruction should be removed from the cache structure based on temporal locality attributes associated with at least one of the first instruction or the second instruction, the temporal locality attributes representing a likelihood that additional requests will be received for an associated instruction while the instruction is stored in the cache structure; removing the first instruction from the cache structure; and storing the second instruction in the cache structure.

Instruction cache management based on temporal locality

An example of a system and method implementing a live migration of a guest on a virtual machine of a host server to a target server is provided. For example, a host server may utilize a flow key to encrypt and decrypt communications with a target server. This flow key may be encrypted using a receive master key, which may result in a receive token. The receive token may be sent to the Network Interface Controller of the host server, which will then encrypt the data packet and forward the information to the target server. Multiple sender schemes may be employed on the host server, and various updates may take place on the target server as a result of the new location of the migrating guest from the host server to the target server.

Managing NIC-encrypted flows for migrating guests or tasks

Growing community of inventors

Sunnyvale, CA, United States of America

Benjamin Charles Serebrin