Netronome Systems Incorporated

Mellanox Technologies, Ltd.

Benjamin Cahill

Gavin J Stark

Mark B Rosenbluth

Carl Ramey

Salma Mirza

Michael Cotsford

Rui Xu

Diane Orf

A multiprocessor device includes cores and at least one ingress-write ordering circuitry (IWOC) including first and second counters associated with first and second destinations. The IWOC is configured to assign sequential numbers to write transactions received from a source, according to an order of reception at the IWOC, and to forward the write transactions from the IWOC to the first and second write-transaction destinations, while preserving the order, by incrementing the first and second counters such that both the first counter and the second counter track a sequential number of a next write transaction that the IWOC will forward, forwarding a first write transaction to the first destination only provided that the sequential number of the first write transaction matches the first counter, and forwarding a second write transaction to the second destination only provided that the sequential number of the second write transaction matches the second counter.

Write reordering in a multiprocessor system

A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

Transactional memory that performs a statistics add-and-update operation

Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. The packet engine uses linear memory addressing to write the packet portions into the memory, and to read the packet portions from the memory.

Packet engine that uses PPI addressing

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Lancaster, MA, United States of America

Benjamin Cahill