Silicon Magnetic Systems

Cypress Semiconductor Corporation

Benjamin C E Schwarz

Kamel Ounadjela

Witold Kula

Eugene Youjun Chen

Sam G Geha

Hanna Bamnolker

Daniel J Arnzen

Chang Ju Choi

Biju Parameshwaran

Helen L Chung

Chan Lon Yan

Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.

Methods for fabricating magnetic cell junctions and a structure resulting and/or used for such methods

A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.

Reducing defect formation within an etched semiconductor topography

A method is provided which includes patterning one or more metal layers arranged above a metal insulating layer and terminating the patterning process upon exposure of the metal insulating layer. In particular, the method may be adapted to be more selective to the metal insulating layer than the one or more metal layers. In general, such an adaptation may include exposing the semiconductor topography to an etch chemistry comprising hydrogen bromide. In some cases, the etch chemistry may further include a fluorinated hydrocarbon. In yet other embodiments, the method may further or alternatively include using a reactive ion etch process, etching at a relatively low temperature, using a resist mask, and/or using an etch chemistry substantially absent of an oxygen plasma. In this manner, the method may, in some embodiments, include patterning the one or more metal layers using a reactive ion etch process substantially absent of an oxygen plasma.

Metal etch process selective to metallic insulating materials

A method for forming a magnetic tunneling junction (MJT) is provided. In some embodiments, the method may include patterning one or more magnetic layers to form an upper portion of a MTJ. The method may further include patterning one or more additional layers to form a lower portion of the MTJ. In some cases, the lower portion may include a tunneling layer of the MTJ having a width greater than the upper portion. In addition, in some embodiments the method may further include patterning an electrode below the lower portion. In some cases, the electrode may include a lowermost layer with a thickness equal to or less than approximately 100 angstroms. In addition or alternatively, the electrode may have a width greater than the width of the tunneling layer. In yet other embodiments, the method may include forming spacers along the sidewalls of the upper and/or lower portions.

Magnetic tunneling junction configuration and a method for making the same

A magnetic random access memory (MRAM) device is provided which includes a conductive line configured to induce a magnetic field with a higher magnitude along at least a portion of a magnetic cell junction than along a spacing arranged adjacent to the magnetic cell junction. In some embodiments, the conductive line may include first portions aligned with a plurality of magnetic cell junctions and second portions aligned with spacings arranged between the plurality of magnetic cell junctions. In such an embodiment, the first portions preferably include different peripheral profiles than the second portions. A method for fabricating such an MRAM device is also provided herein. The method may include aligning magnetic cell junctions and first portions of a field-inducing line with each other such that at least part of the first portions of the field-inducing line are configured to conduct a higher density of current than second portions of the field-inducing line.

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Sunnyvale, CA, United States of America

Benjamin C E Schwarz