International Business Machines Corporation

Qualcomm Incorporated

Mentor Graphics Corporation

Benjamin Bowers

Anthony Correale, Jr

Matthew Wayne Baker

Paul Michael Steinmetz

Irfan Rashid

Nishith Rohatgi

William Goodall, Iii

Douglass T Lamb

Tracey Della Rova

Giridhar Nallapati

Gregory Christopher Burda

Chock Hing Gan

William Robert Flederbach

Robert J Bucki

Matthew D Youngblood

James W Hayward

Charanya Gopal

Ohsang Kwon

Satyanarayana Sahu

David Paul Hoff

Michael B Mitchell

Joshua Lance Puckett

Milind Ram Kulkarni

Nicole Marie Arnold

Anthony L Polomik

Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.

Standard cell architecture for diffusion based on fin count

Systems and methods relate to cell placement methodologies for improving length of diffusion of transistors. For example, a first transistor with a first diffusion node which is bounded by a first diffusion cut is identified in a transistor level layout. The first diffusion cut is replaced with a first floating gate, and a first filler cell with a first filler diffusion region is added to extend a length of diffusion of the first diffusion node. Increasing the length of diffusion leads to improving drive strength and performance of the first transistor.

Mitigating length-of-diffusion effect for logic cells and placement thereof

Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.

Efficiently generating selection masks for row selections within indexed address spaces

Embodiments that design integrated circuits using a 1&#xd7;N compiler in a closed-loop 1&#xd7;N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1&#xd7;N building blocks. The embodiments may alter elements of the 1&#xd7;N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1&#xd7;N building block elements.

Compiler for closed-loop 1&#xd7;N VLSI design

At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain.

Continuous diffusion configurable standard cell architecture

A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Method and apparatus for a diffusion bridged cell library

Compiler for closed-loop 1xN VLSI design

Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.

Methods, systems, and media to improve manufacturability of semiconductor devices

Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.

Creating integrated circuit capacitance from gate array structures

Embodiments that create parent-child relationships for reuse of 1&#xd7;N building blocks in a closed-loop 1&#xd7;N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1&#xd7;N building block into the representation, and creating an association between the first 1&#xd7;N building block and a second 1&#xd7;N building block. The association enables the first 1&#xd7;N building block to inherit alterations of attributes of the second 1&#xd7;N building block and enables unique alterations of attributes of the first 1&#xd7;N building block which differ from the second 1&#xd7;N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1&#xd7;N building blocks, an attribute creator that creates a set of attributes and enables one of the 1&#xd7;N building blocks to inherit parent attributes and comprise child attributes.

Uniquification and parent-child constructs for 1xN VLSI design

Embodiments that make DFM alterations to cells of 1&#xd7;N building blocks via a closed-loop 1&#xd7;N compiler are disclosed. Some embodiments comprise using a 1&#xd7;N compiler to detect a relationship between two adjacent cells of a 1&#xd7;N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1&#xd7;N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.

Growing community of inventors

Cary, NC, United States of America

Benjamin Bowers