Infineon Technologies Ag

Beng Keh See

Chau Fatt Chiang

Horst Theuss

Joachim Mahler

Ulrich Krumbein

Swee Kah Lee

Helmut Wietschorke

Kok Yau Chua

Soon Lock Goh

Mei Chin Ng

Stefan Martens

Sook Woon Chan

Tze Yang Hin

Guan Choon Matthew Nelson Tee

Christian Geissler

Bernd Goller

Dominic Maier

Thomas Kilger

Chee Yang Ng

Daniel Kehrer

Werner Simbuerger

Johannes Lodermeyer

Matthias Steiert

Claus Waechter

Franz-Xaver Muehlbauer

Chwee Lan Lai

A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.

Manufacturing a package using plateable encapsulant

A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.

Semiconductor package with a through port for sensor applications

A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.

Semiconductor package with plateable encapsulant and a method for manufacturing the same

In various embodiments, a chip arrangement may be provided. The chip arrangement may include a metallic carrier. The chip arrangement may also include at least one chip arranged on the metallic carrier, wherein the at least one chip includes a chip contact, wherein the chip contact is electrically coupled to the metallic carrier. The chip arrangement may also include encapsulation material at least partially encapsulating the at least one chip. The chip arrangement may also include an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier.

Chip arrangement and a method of manufacturing a chip arrangement

A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Module and method of manufacturing a module

In one embodiment a method for manufacturing a semiconductor device comprises arranging a wafer on a carrier, the wafer comprising singulated chips; bonding the singulated chips to a support wafer, and removing the carrier.

Method of manufacturing a semiconductor device

A method for producing multiple semiconductor devices. An electrically conductive layer is applied onto a semiconductor wafer. The semiconductor wafer is structured to produce multiple semiconductor chips. The electrically conductive layer is structured to produce multiple semiconductor devices.

Method of producing multiple semiconductor devices

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Melaka, Malaysia

Beng Keh See