Advanced Micro Devices Corporation

Beng Chew Khou

Jacques Ah Wong

Boon Piaw Tan

Sie Boo Chiang

Reuben A Aspacio

Joon Kit Goh

Leok Saw Chua

A method for synthesizing a register transfer level (RTL) based design employs a bottom-up approach to generate a final top-level design. The top-level design is divided into a plurality of sub-modules. Each of the sub-modules is then independently synthesized using an RTL based design approach and independently adapted to conform to timing requirements produced for each of the sub-modules using time budgets that are based on the top-level timing requirements. Once the sub-modules are synthesized and pass individual timing requirements specific for those sub-modules, the sub-modules are integrated to form a top-level design. The top-level design may then be verified for timing requirements and other formal requirements.

Bottom-up approach for synthesis of register transfer level (RTL) based design

A method and arrangement for testing different types of external memories that can be coupled to a network interface controller. The network interface controller interprets the results of the memory test differently in accordance with the memory type. A fail state indicator is used by test controller to indicate the proper offset to add or subtract to a test address to calculate the actual failing memory location.

Method and apparatus for exercising external memory with a memory built-in self-test

An arrangement and method of performing a memory built-in self test (MBIST) on a memory loops together the registers that store the MBIST results. When an error is detected during the MBIST by an MBIST controller, the MBIST results are shifted serially through the register loop as well as off the chip performing the MBIST. Once all the MBIST results are shifted out for further analysis by a host computer, for example, the MBIST controller is in its original state at the time the error was detected as the MBIST results are back in the registers they occupied prior to the shifting out of the MBIST results off the chip.

Method and apparatus for looping back a current state to resume a memory built-in self-test

A method and arrangement for performing a memory built-in self test (MBIST) of an external memory and an internal memory of a network interface controller includes a series of burst write and burst read operations if an external memory is detected. The sequence of burst operations tests the back-to-back burst write, back-to-back burst write burst read, back-to-back burst read and back-to-back burst read burst write capabilities of the external memory, to thereby fully exercise the external memory. Additionally, the internal memory is tested by single write and single read accesses.

A method for testing and verifying an integrated circuit using a bottom-up approach to generate a complete integrated circuit. The design for an integrated circuit is divided or defined into individual sub-system modules which are then tested either individually or as a combination of sub-system modules (e.g., a partially integrated circuit). Once all of the sub-system modules are tested and verified, the sub-system modules can be combined to form a complete integrated circuit which can then be tested. Each of the sub-system modules, the partially integrated circuit and the complete integrated circuit are tested and verified.

Method for faster verification of a design for an integrated circuit

A network interface device is provided with a memory controller to control data writing and reading to and from an external synchronous SRAM. An interface to the SRAM has a clock pad responsive to an internal clock signal to produce a SRAM clock sent to the SRAM as a reference clock to support access to the SRAM. The clock pad contains an inverter for inverting the internal clock signal so as to produce the SRAM clock in response to the inverted internal clock signal. As a result, read time allocated for reading data from the SRAM to the memory controller is made longer than a cycle of the internal clock signal.

Clocking to support interface of memory controller to external SRAM

A flip-flop for storing a bit of digital information generally used in register architectures is comprised of a two-input NAND gate and a D-type flip-flop. The output of the NAND gate is connected to the clock terminal of the flip-flop and the data signal is directed to the data terminal of the flip-flop. A new clock scheme is provided with for this circuit configuration in order to properly store the data signal.

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Beng Chew Khou