Delta Electronics Int'l (singapore) Pte Ltd

Beng Beng Lim

Xiaofeng Xu

Chien-Ming Chen

Jie Song

Yiu Wai Lai

A package structure includes a first encapsulation member, a second encapsulation member, at least one semiconductor chip, a plurality of metal pins and a second insulation layer. The first encapsulation member includes a first metal layer, a first insulation layer and a second metal layer. The at least one semiconductor chip is disposed between the first encapsulation member and the second encapsulation member. The at least one semiconductor chip comprises a plurality of conductive terminals connected with the first metal layer or a third metal layer. The plurality of metal pins are disposed between and extended outward from the first encapsulation member and the second encapsulation member. The second insulation layer is disposed between the first encapsulation member and the second encapsulation layer for securing the first encapsulation member, the second encapsulation member, the at least one semiconductor chip, and the plurality of metal pins.

Heat-dissipating semiconductor package including a plurality of metal pins between first and second encapsulation members

A packaging process and a packaging structure of an electronic component are provided. By the packaging process and the packaging structure of the disclosure, the groove of the thermal conduction structure is covered by the first metal re-distribution layer. Therefore, the flank of the thermal conduction structure is easy to coat the conducting material. Moreover, because the flank of the thermal conduction structure is coated, the surface of the flank of the thermal conduction structure is difficultly oxidized. Furthermore, the conducting material between the thermal conduction structure and the board is flat, so that automated optical inspection of the packaging structure is easy to implement.

Packaging process and packaging structure

A packaging process and a packaging structure of an electronic component are provided. By the packaging process and the packaging structure of the disclosure, the groove of the thermal conduction structure is covered by the first metal re-distribution layer. Therefore, the flank of the thermal conduction structure is easy to coat the conducting material. Moreover, because the flank of the thermal conduction structure is coated, the surface of the flank of the thermal conduction structure is difficulty oxidized. Furthermore, the conducting material between the thermal conduction structure and the board is flat, so that automated optical inspection of the packaging structure is easy to implement.

A package structure and a manufacturing method thereof are provided. The package structure includes an insulation layer, an electronic component and a lead frame unit. The electronic component is embedded within the insulation layer and includes plural conducting terminals. The lead frame unit is embedded within the insulation layer and includes a lead frame and a metallization layer. The metallization layer having a thickness more than 10 &#x3bc;m is disposed on at least a part of the lead frame and electrically connected with at least one of the plural conducting terminals of the electronic component.

Package structure and manufacturing method thereof

A package structure includes a first insulation layer, a first redistribution structure, at least one electronic component, a second redistribution structure, a second insulation layer, a first heat spreader, a heat dissipation substrate, a second heat spreader and plural thermal conduction structures. A part of the second redistribution structure is disposed on a part of a top surface of the first insulation layer, and the other part of the second redistribution is located in the first insulation layer. At least one of the conducting terminals is connected with the second redistribution structure. At least one of the thermal conduction structures is connected with at least one of the first redistribution structure and the second redistribution structure, and the thermal conduction structures are respectively extended outwardly from the opposite sides of the first insulation layer to form pins.

Package structure and power module using same

A packaging process of an electronic component is provided. By the packaging process of the disclosure, the electronic component is grinded by the back grinding process. Consequently, thickness of the electronic component may be reduced to less than or equal to 50 &#x3bc;m. The packaging process may achieve ultra-thin thickness and reduce the space of the power module. Moreover, the packaging process forms the contact pads with drilling process and grinding process without photolithography process. Consequently, the packaging process is advantageous because of lower cost and uniform thickness of the contact pads.

Packaging process

A package structure includes an insulation layer, an electronic component, at least one thermal conduction structure, a first re-distribution block and a heat dissipation device. The electronic component is embedded within the insulation layer, and comprises a first surface exposed from a top surface of the insulation layer, a second surface and plural conducting terminals formed on the second surface. The at least one thermal conduction structure is embedded within the insulation layer and partially exposed from the top surface of the insulation layer. One part of the first re-distribution block is disposed on a bottom surface of the insulation layer, and the other part of the first re-distribution block is located in the insulation layer and connected with the at least one thermal conduction structure and at least one of the conducting terminals. The heat dissipation device is mounted onto the first surface of the electronic component.

Dual side cooling structure

A first insulation layer comprising stacked prepreg layers is provided, and a metallic protective layer is formed on the first insulation layer. A first alignment mark is formed on the first insulation layer, and an accommodation cavity is formed in the first insulation layer according to the first alignment mark. A second alignment mark is formed on the first insulation layer according to the first alignment mark. A carrier plate is attached on the first insulation layer through a thermal release tape layer, and the semiconductor device is temporarily fixed on the thermal release tape layer within the accommodation cavity according to the second alignment mark. A semi-cured second insulation layer is placed over the first insulation layer, and the second insulation layer is laminated and cured. A re-distribution layer is formed on the second insulation layer, and the re-distribution layer is electrically connected with the semiconductor device.

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Singapore, Singapore

Beng Beng Lim