Integrated Device Technology, Inc.

Nxp B.v.

Benedykt Mika

Brian Jeffrey Buell

Amrita Deshpande

Pengfei Hu

Ron Osgood

Chen-Wei Huang

Rohini Abhyankar

Ragu Sridhar

An inductor is disclosed that includes an arrangement of lobes, each of the lobes in the arrangement of lobes including a generator, the arrangement of lobes interconnected such that, when currents are provided by each generator in the arrangement of lobes, each lobe in the arrangement of lobes produces a magnetic field with a defined polarity relative to the arrangement of lobes. When the arrangement of lobes are appropriately interconnected, the magnetic field from the arrangement of lobes can be canceled.

Active twisted figure '8' inductor

Integrated circuit devices include programmable dividers, such as fractional-N dividers, which can utilize multi-modulus dividers (MMD) therein. A multi-modulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P&#x3c;n:0&#x3e; during an update time interval and may even fully turn off one or more of the div2/3 cells not participating in a divide-by-N operation, where N is a positive integer greater than one. The div2/3 cells are configured to include a modulus input terminal and a modulus output terminal and the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.

Self-adaptive multi-modulus dividers containing div2/3 cells therein

Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.

Fractional-N dividers having divider modulation circuits therein with segmented accumulators

Methods and systems directed toward a PLL circuit including a local lock detector receiving an error signal and providing a lock signal, and a charge pump for receiving the error signal and providing a charge signal. A loop filter provides a first loop filter bandwidth and a second loop filter bandwidth. The loop filter includes a first low-pass filter configured to receive the charge and lock signals, alter a filter characteristic in response to the lock signal, and provide a first filter signal. The loop filter includes a second low-pass filter configured to receive the first filter and lock signals, alter a filter characteristic in response to the lock signal, and provide a loop filter signal. The PLL circuit includes a VCO for receiving the loop filter signal and providing an output signal, and a divider for receiving the output signal and dividing it to provide the reference signal.

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Chandler, AZ, United States of America

Benedykt Mika