Advanced Micro Devices Corporation

Qualcomm Incorporated

Stmicroelectronics Gmbh

Benedict R Gaster

Lee W Howes

Michael C Houston

Michael Mantor

Bradford Michael Beckmann

Steven Karl Reinhardt

David Allen Wood

Richard Shann

Mark Douglas Hummel

Brian D Emberling

Mark Donald Hill

Mark M Leather

Alan Bryant Heirich

Jayanth Gummaraju

Marc S Orr

Norman Rubin

Derek R Hower

Blake A Hechtman

Stephen Clarke

Laurent Morichetti

Sean McGoogan

Con Bradley

Dominik Behr

With the success of programming models such as OpenCL and CUDA, heterogeneous computing platforms are becoming mainstream. However, these heterogeneous systems are low-level, not composable, and their behavior is often implementation defined even for standardized programming models. In contrast, the method and system embodiments for the heterogeneous parallel primitives (HPP) programming model disclosed herein provide a flexible and composable programming platform that guarantees behavior even in the case of developing high-performance code.

Heterogeneous parallel primitives programming model

A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to a next instruction following the synchronization instruction in the instruction stream to be executed by the first workitem. A second workitem is run on the processor after the yielding.

Method and system for yield operation supporting thread-like behavior

A processor comprising hardware logic configured to execute of a first wavefront in a hardware resource and stop execution of the first wavefront before the first wavefront completes. The processor schedules a second wavefront for execution in the hardware resource.

Wavefront resource virtualization

A system, method, and computer program product are provided for improving resource utilization of multithreaded applications. Rather than requiring threads to block while waiting for data from a channel or requiring context switching to minimize blocking, the techniques disclosed herein provide an event-driven approach to launch kernels only when needed to perform operations on channel data, and then terminate in order to free resources. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.

Multithreaded computing

A portable computing device synchronously offloads tasks from a first processing resource to an alternative processing resource. Offload requests are centralized and communicated to a dispatch controller. The request defines the alternative processing resource and the location of items in a common or shared memory related to a thread that is desired to be transferred or dispatched from the primary processing resource to the identified alternative processing resource. The dispatch controller, in response to the request, creates a task dispatch packet that provides the information required to switch the context of the thread that was previously executing on the primary processing resource to the alternative processing resource. The common or shared memory space is leveraged to provide desired performance. Results generated by the alternative processing resource are available in the shared memory space upon return to the primary processing resource.

System and method for synchronous task dispatch in a portable device

Some embodiments include a processing subsystem that compiles program code to generate compiled program code. In these embodiments, while compiling the program code, the processing subsystem first identifies a pointer in the program code that points to an unspecified address space. The processing subsystem then analyzes at least a portion of the program code to determine one or more address spaces to which the pointer may point. Next, the processor updates metadata for the pointer to indicate the one or more address spaces to which the pointer may point, the metadata enabling a determination of an address space to which the pointer points during subsequent execution of the compiled program code.

Handling pointers in program code in a system that supports multiple address spaces

Disclosed methods, systems, and computer program products embodiments include synchronizing a group of workitems on a processor by storing a respective program counter associated with each of the workitems, selecting at least one first workitem from the group for execution, and executing the selected at least one first workitem on the processor. The selecting is based upon the respective stored program counter associated with the at least one first workitem.

Method and system for synchronization of workitems with divergent control flow

A method, computer program product, and system is described that determines the correctness of using memory operations in a computing device with heterogeneous computer components. Embodiments include an optimizer based on the characteristics of a Sequential Consistency for Heterogeneous-Race-Free (SC for HRF) model that analyzes a program and determines the correctness of the ordering of events in the program. HRF models include combinations of the properties: scope order, scope inclusion, and scope transitivity. The optimizer can determine when a program is heterogeneous-race-free in accordance with an SC for HRF memory consistency model. For example, the optimizer can analyze a portion of program code, respect the properties of the SC for HRF model, and determine whether a value produced by a store memory event will be a candidate for a value observed by a load memory event. In addition, the optimizer can determine whether reordering of events is possible.

Method for memory consistency among heterogeneous computer components

A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads into one or more workgroups, associating a first workgroup from the one or more workgroups with an operating system thread on the processor core, and configuring threads from the first workgroup as user-level threads within the operating system thread. In an example, a method enables the execution of GPU-kernels that has been previously configured for a GPU, to execute on a CPU such as a multi-core CPU. The mapping of the numerous data-parallel threads to the CPU is done in such a manner as to reduce the number of costly operating system threads instantiated on the CPU, and to enable efficient debugging.

Mapping processing logic having data-parallel threads across processors

In a computing system, memory may be managed by using a distributed array, which is a global set of local memory regions. A segment in the distributed array is allocated and is bound to a physical memory region. The segment is used by a workgroup in a dispatched data parallel kernel, wherein a workgroup includes one or more work items. When the distributed array is declared, parameters of the distributed array may be defined. The parameters may include an indication whether the distributed array is persistent (data written to the distributed array during one parallel dispatch is accessible by work items in a subsequent dispatch) or an indication whether the distributed array is shared (nested kernels may access the distributed array). The segment may be deallocated after it has been used.

Allocating memory and using the allocated memory in a workgroup in a dispatched data parallel kernel

A sequencer of a processing unit determines, at runtime, a barrier width of a barrier operation for a group threads, wherein the barrier width is smaller than a total number of threads in the group of threads, and wherein threads in the group of threads execute data parallel code on one or more compute units. In response to each thread in a subgroup of the group of threads having executed the barrier operation, the subgroup including a same number of threads as the barrier width, the sequencer may enable the subgroup of the group of threads to execute on the one or more processors past the barrier operation without waiting for other threads in the group of threads to execute the barrier operation, wherein the subgroup of the group of threads is smaller than the total number of threads in the group of threads.

Growing community of inventors

Santa Cruz, CA, United States of America

Benedict R Gaster