International Business Machines Corporation

Arris Group, Inc.

Arris Enterprises LLC

Arris Solutions, Inc.

Benedict Joseph Jackson

Marcel F Schemmann

Paul Edward McKenney

Ramakrishnan Rajamony

Ronald Lynn Rockhold

Zoran Maricevic

Zhijian Sun

Christopher A Provenzano

William A Braun

Carl H Seaton

Eric Cormier

Jayesh Bhatt

Michael N Galassi

A network device provides output data rate control having variable bandwidth and a response time constant that increases according to an amount of time that an input rate of data to the network device is evaluated by the logic to provide output data rate control. The device applies a rate estimate when a determination of the output rate to a predetermined accuracy is unavailable.

Flow control in a network device

A process of scheduling stream packets for output from a multiplexing network device involves prioritizing the output of packets first according to stream priority, and within a particular priority, by stream ID.

A process involves controlling an output rate of a network device using rate control logic, and providing a variable bandwidth for the rate control logic and increasing a response time constant of the rate control logic according to an amount of time that an input rate of data to the network device is evaluated by the rate control logic; applying a rate estimate when a determination of the output rate to a predetermined accuracy is unavailable; applying a time rate determined from the difference in two PCR packets otherwise; and applying the time rate determined from the difference in two PCR packets unless the rate estimate shows that an actual rate has changed to an extent that triggers a change in the output rate to the rate estimate.

A system includes logic to cache at least one block in at least one cache if the block has a popularity that compares favorably to the popularity of other blocks in the cache, where the popularity of the block is determined by reads of the block from persistent storage and reads of the block from the cache.

Caching of information according to popularity

A channel alignment system in an optical communication network includes logic to sample power of a quadrature amplitude modulation (QAM) channel at a component downstream from a QAM modulator. The system determines if the sampled channel power has a sufficient level. The system signals power control logic of the QAM modulator to adjust a gain of the sampled channel.

Dual use of test point power monitor

A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.

Quad aware locking primitive

A RAID storage system includes an outer stripe size that is an integer multiple J of a product of an inner stripe size and a number of data disks in a RAID disk set, where J is greater than one (1).

RAID stripe layout scheme

A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy, and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. Accordingly, efficiency of a computer system may be enhanced with the ability to utilize a locking primitive for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection.

A method for a computation agent to acquire a queue lock in a multiprocessor system that prevents deadlock between the computation agent and external interrupts. The method provides for the computation agent to join a queue to acquire a lock. Next, upon receiving ownership of the lock, the computation agent raises its priority level to a higher second priority level. In response to a receipt of an external interrupt having a higher priority level occurring before the computation agent has raised its priority level to the second higher priority level, the computation agent relinquishes ownership of the lock. Subsequent to raising its priority level to the second higher priority level, the computation agent determines if it still has ownership of the lock. If the computation agent determines that it has not acquired possession of the lock after raising its priority level, the computation agent rejoins the queue to reacquire the lock. In one embodiment of the present invention, the computation agent's priority level is restored to its original, i.e., first priority level, when it rejoins the queue to reacquire the lock.

Growing community of inventors

Beaverton, OR, United States of America

Benedict Joseph Jackson