Rambus Inc.

Benedict C Lau

Huy M Nguyen

Jade M Kizer

Roxanne T Vu

Leung Yu

Bret G Stott

Ian P Shaeffer

Vijay Gadde

Sivakumar Doraiswamy

Chanh Vi Tran

Donald C Stark

Kevin S Donnelly

Bruno Werner Garlepp

Pak Shing Chau

Yiu-Fai Chan

Craig Edward Hampel

Mark A Horowitz

Stefanos Sidiropoulos

Thomas H Lee

Mark G Johnson

James A Gasbarro

Jun Y Kim

Nhat M Nguyen

Adam Chuen-Huei Chou

Huey M Nguyen

John Welsford Brooks

Eugene C Ho

Philip Yeung

Bradley A May

Tsyr-Chyang Ho

Jason C Wei

Clemenz L Portmann

Yueyong Wang

Chuen-Huei Chou

Samir A Patel

Huy Nguyen

A memory controller includes a register to store phase offset value. The phase offset value represents a phase relationship between a memory request signal component and a reference signal. The phase offset value is established through write and read back testing. Transmit circuitry applies the phase offset value in launching the memory request signal component from the IC memory controller to an IC memory device.

Memory controller with staggered request signal output

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Memory controller for strobe-based memory systems

A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship been the control signal and the timing signal.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Calibration methods and circuits to calibrate drive current and termination impedance

A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship between the control signal and the timing signal.

Memory device with circuitry to transmit feedback indicative of a phase relationship

A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

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San Jose, CA, United States of America

Benedict C Lau