Matrix Semiconductor, Inc.

Microchip Technology Inc.

Zerog Wireless, Inc.

Sandisk 3d LLC

Intel Corporation

Lucent Technologies Inc.

Mosys, Inc.

Other

Leland Stanford Junior University

Sandisk Corporation

Bendik Kleveland

Roy E Scheuerlein

Thomas H Lee

James Montague Cleeves

Mark G Johnson

Alper Ilkbahar

N Johan Knall

Stanley Wang

Gunes Aybay

Luca Giovanni Fasoli

Philip Arnold Ferolito

Eric T Anderson

Jay B Patel

Rajesh Chopra

Dipak Sikdar

Christopher S Moore

Matthew P Crowley

Roger March

Feng Li

Xiaoyu Yang

Kenneth K So

Chia Yang

Carl Gyllenhammer

Seung Yu

Michael Palladino

Yuen Hui Chee

Tae Hee Lee

N Johann Knall

A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.

Memory device with background built-in self-repair using background built-in self-testing

A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.

Memory device with background built-in self-testing and background built-in self-repair

The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.

Virtual memory interface

A hybrid circuit () for use with communications transceivers. The hybrid circuit () combines the function of an ESD protection circuit () with the function of a TX/RX switch (). The input node of the hybrid circuit () is connecting between the source of an ESD event () and a device to be protected (). The hybrid circuit () includes an ESD protection element (), which is triggered by a triggering transistor (). The gate of the triggering transistor () is connected to a driver () for turning the triggering transistor () on during transmission and for turning the triggering transistor () off during reception.

Hybrid circuit for circuit protection and switching

A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulatorreceives an input voltage on Vfrom a battery or some other power supply at node Vand supplies a stable regulated voltage to load deviceat node V. Load devicepulls different amounts of current and requires different degrees of tolerance on the voltage at Vdepending upon its operating conditions. Data collection and control circuitis capable of enabling and disabling regulatorand regulator. Data collection and control circuitis also capable of measuring certain performance parameters associated with load deviceand the operating conditions of load device. Data collection and control circuitenables regulatorif said operating conditions are such that when data collection and control circuitenables regulatorthe performance parameters associated with loadare below a predefined standard.

Regulator with device performance dynamic mode selection

A calibration circuit () and method () for calibrating the bias current of a VCO () to minimize phase noise. The calibration circuit () monitors the average voltage at the common-mode node of the VCO () while varying the bias current over a predetermined range. The calibration circuit () identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO ().

Calibration of voltage controlled oscillators

A voltage regulator circuit and method are provided for regulating a voltage accurately in response to rapid variations in the regulator's load. The voltage regulator utilizes a hybrid loop; an embodiment of such utilization is exemplified by circuit. Amplifiercontrols the current flowing through pass elementfrom an unregulated input voltage node Vto a regulated voltage output node V. The regulated output voltage is provided to loadso that the voltage across the load stays constant regardless of variations in the current it pulls. The value of the regulated voltage is set by feedback networkand the input voltage at node V. The regulator feedback loop formed by amplifier, pass element, and feedback networkregulate the voltage at Vin response to low frequency perturbations in load. In response to high frequency perturbations, a sensing network triggers control circuitry. Such a sensing network is exemplified in this embodiment by comparatorsand. In response to a trigger signal, the control circuitry adjusts the drive capability of pass elementto rapidly return Vto its regulated value. When the voltage at Vreturns to its regulated value the drive capability of pass elementis reset.

Voltage regulator with a hybrid control loop

An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance. In the second state, each of the memory cells includes a rectifying junction between the respective diffused well region and the respective electrical conductor.

One-time programmable non-volatile memory

A startup circuitand methodis provided for quickly starting up a resonator based oscillator. Tunable oscillatorprovides an impetus signal to oscillatorthrough capacitor. The impetus signal has a frequency that is an estimate of the resonant frequency of resonator. The circuit measures the frequency of oscillatorand the frequency of tunable oscillator. The circuit then adjusts the frequency of tunable oscillatorsuch that the frequency of the tunable oscillator is substantially equal to the resonant frequency of the resonatorand stores a data state necessary for the tunable oscillatorto generate a signal with this target frequency in the future. During an ensuing startup cycle the stored data state causes the impetus signal delivered by tunable oscillatorto be substantially equal to the target frequency of oscillatorwhich improves startup performance.

Fast startup resonant element oscillator

Calibration of voltage-controlled oscillators

In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.

System architecture and method for three-dimensional memory

The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of memory cells and a redundant block of memory cells. In response to an error in writing to the primary block, a flag is stored in a set of memory cells allocated to the primary block, and the redundant block is written into. In another preferred embodiment, an error in writing to a primary block is detected while an attempt is made to write to that block. In response to the error, the redundant block is written into. In yet another preferred embodiment, a memory device is provided comprising a three-dimensional memory array and redundancy circuitry. In still another preferred embodiment, a method for testing a memory array is provided. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Memory device and method for redundancy/self-repair

A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.

Method and apparatus for programming a memory array

A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single-ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.

High-speed chip-to-chip communication interface

Growing community of inventors

Santa Clara, CA, United States of America

Bendik Kleveland