Synopsys, Inc.

Ben Mathew

Sabyasachi Das

Gary K Yeap

KunMing Ho

Renu Mehra

Bang Liu

Xiao-Ming Xiong

Jin Wu

Hung-Chun Chien

Padmashree Takkars

Chang-Wei Tai

A system to generate a design of an integrated circuit, the system comprising a memory and a processor, the processor to define a plurality of voltage area regions (VARs), based on an availability of one or more of a primary power source and one or more secondary power sources. The processor further to constrain placement and/or routing of an element in the design of the integrated circuit within a voltage area region of the plurality of voltage area regions defined by secondary power/ground (PG) constraints based on power requirements of the element.

Method to perform secondary-PG aware buffering in IC design flow

Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.

Design-for-test-aware hierarchical design planning

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Plano, TX, United States of America

Ben Mathew