International Business Machines Corporation

Ben Jesse Nathanson

Dong Chen

Paul William Coteus

Alan G Gara

Gerard Vincent Kopcsay

Wayne Melvin Barrett

Rory D Jackson

Todd Edward Takken

Pavlos Michael Vranas

Carl Alfred Bender

Gerard M Salem

Gordon Wesley Braudaway

Richard A Swetz

Paylos Michael Vranas

Singpui Zee

A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

Data capture technique for high speed signaling

An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance with the communication protocol, and wherein the first and second DMA engines transfer data for the packets independently of each other.

System for independently transferring data using two independently

An inter-processor interrupt mechanism is implemented in a shared-memory multi-processor system. A dedicated halfword for each processor in said multi-processor system is provided in the shared memory restricted in use to the generation and control of inter-processor interrupts. No data in any dedicated shared-memory location can be altered by any processor unless it has 'captured' the location by executing a test and set halfword instruction and a captured shared-memory location being released only by executing a store halfword instruction. An address comparator and a zero detector are added as adjunct operations to read-modify-write logic of each processor's memory interface. When any instruction is executed and its operand address agrees with that contained in the address comparator, an inter-processor interrupt request is generated if zero is not detected on all predefined data bits being written to memory. If a zero is detected on all predefined data bits being written to memory, the inter-processor interrupt request is removed.

Method and apparatus for implementing inter-processor interrupts using

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Teaneck, NY, United States of America

Ben Jesse Nathanson