Xilinx, Inc.

Ben J Jones

Gordon I Old

Jeffrey Allan Graham

William A Wilkie

Colin Stirling

Jonathan Castelli

Methods and apparatus for detecting alignment markers in received data streams received via a plurality of data lanes are disclosed. Corresponding data streams may be received via respective data lanes in the plurality of data lanes, where each data stream includes alignment markers delineating data frames, and each alignment marker has a predefined bit pattern. For each respective data lane, a determination is made whether a specified portion of the received data stream has at least a threshold degree of similarity with a portion of the predefined bit pattern. In response to determining, for one of the plurality of data lanes, that the specified portion has at least the threshold degree of similarity, a frame boundary may be determined based on the specified portion, and a verification may be performed, that the specified portion of the received data stream corresponds to an alignment marker.

Identifying alignment markers using partial correlators

An apparatus and method for determining an alignment of a codeword is disclosed. A data stream may be received, and a cumulative syndrome value determined. The cumulative syndrome value may be based on error correction and data scrambling operations performed on the data stream. If the cumulative syndrome value matches a predetermined cumulative syndrome value, then alignment of the codeword with respect to the data stream is determined.

Method and apparatus for codeword alignment

A forward error correction decoder for packing error information of a codeword in the space that was previously occupied by the parity symbols in the decoder output is presented. Specifically, the decoder summarizes error information of the codeword in a summary vector having the size no greater than the total size of the parity symbols. The decoder then outputs the message symbols from the codeword and the summary error vector, which provides the error information of the received codeword but only requires a bandwidth that is no greater than the bandwidth previously used for transmitting the parity symbols.

System and method for a forward error correction decoder with error reporting

Techniques for handling synchronization headers for serial data transmission with multi-level signaling are described. In an example, a transmitter includes a multiplexer circuit configured to serialize an input signal to generate an output bit sequence having a plurality of bits between pairs of synchronization header bits. The transmitter includes a re-ordering circuit, coupled to the multiplexer circuit to receive the output bit sequence, configured to re-order the output bit sequence by moving at least one of the plurality of bits between the synchronization header bits in each of the pairs of synchronization header bits. The transmitter includes an output driver circuit configured to drive the re-ordered output bit sequence onto a transmission medium.

Synchronization headers for serial data transmission with multi-level signaling

Apparatus and method for communication is disclosed. In an apparatus, at least one transmission circuit is configured to provide an output alignment marker representing an exclusive disjunction of an orthogonal sequence and an input alignment marker. A multiplexer is configured to multiplex the output alignment marker with payload data for transmission via a communication lane of a plurality of communication lanes.

Alignment marker generation and detection for communication

An apparatus and method therefor for a receiver are disclosed. In this apparatus, at least one delay line is configured to receive input data from a communication lane and provide repetitions of the input data delayed with respect to one another. An exclusive disjunction combinatorial circuit is configured to receive the input data and the repetitions thereof and to generate a discontinuity-detection signal for codeword alignment responsive to successive linear combination by exclusive disjunction of the input data and the repetitions thereof to cancel out portions of repeated sequences of the input data for detection of at least one type of discontinuity in the input data.

Alignment marker independent data alignment for a receiver

In an example implementation, an alignment detection circuit includes a buffer, a candidate selection circuit, and a correlator circuit. The buffer is configured to receive a data stream from a data lane, the data stream including alignment markers delineating data frames, each of the alignment markers having a predefined bit pattern. The candidate selection circuit is configured to identify candidate data blocks in successive data blocks of the data stream provided by the buffer, each of the candidate blocks having a measure of symmetry satisfying a threshold metric indicative of the predefined bit pattern. The correlator circuit is configured to search for at least one of the alignment markers in each of the candidate blocks and adjust alignment of the data stream in the buffer in response to locating the at least one alignment marker.

Alignment detection in a multi-lane network interface

A decoder in a device receiving data having an error correction code is described. The decoder comprises a memory storing program code having instructions including control signals for decoding an error correction code; an address generator coupled to the memory, the address generator updating an address coupled to the memory for generating a next control signal; and a data processing circuit coupled to receive an instruction from the memory and further coupled to receive syndrome data, the data processing circuit generating error correction values. A method for decoding data having an error correction code is also disclosed.

Decoder in a device receiving data having an error correction code and a method of decoding data

A circuit enabling generating a product in a decoder circuit is disclosed. The circuit comprises a first memory element coupled to receive a first error value and a first portion of a second error value; a second memory element coupled to receive the first error value and a second portion of the second error value; and an adder circuit coupled to add an output of the first memory element and an output of the second memory element. The output of the first memory element is generated in response to an address based on the first error value and the first portion of the second error value, and the output of the second memory element is generated in response to an address based on the first error value and the second portion of the second error value. A method for generating a product in a decoder circuit is also disclosed.

Circuit enabling and a method of generating a product in a decoder circuit

For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for output from at least one phase responsive to at least the at least one address; first update of the at least one address as being equal to summation of the at least one increment and the at least one address modulo the block size; and second update of the at least one increment as being equal to summation of the at least one increment and the step value modulo the block size. The selection and the first and second updates are iteratively repeated responsive to increments of the count index to output a sequence of addresses.

Address generation for quadratic permutation polynomial interleaving

Method, apparatus, and computer readable medium for producing an optimized matrix triangulation algorithm is described. In one example, tile functions are generated for a matrix triangulation problem. Cost data is measured for the tile functions with respect to a target architecture. The cost data is processed to identify optimal composition of tiles for rows in an iteration space of the matrix triangulation problem. The optimal compositions of tiles are processed to identify optimal composition of rows for triangles in the iteration space. A sequence of tile function invocation based on the optimal compositions of tiles and the optimal compositions of rows is generated.

Method and apparatus for producing optimized matrix triangulation routines

Apparatus for vector generation is described. A vector generator is associated with a discrete power series symmetric about at least one term and configured to provide vectors, such as QSvectors for a Turbo Code for example. The vectors are each provided in separate portions as a first portion and a second portion. The second portion of a vector of the vectors is generated from the first portion of the vector using symmetry about the at least one term.

Vector generation for codes through symmetry

According to one aspect of the invention, a method of interleaving data for enabling data coding in a communication network is disclosed, the method including storing parameters required to output address sequences for a matrix, receiving a block size associated with a block of data at a circuit for interleaving data, outputting parameters associated with the stored parameters based upon the block size, and producing an address sequence using the parameters. A circuit for interleaving data for data coding in a communication network is also disclosed. The circuit includes a lookup table storing parameters required to output address sequences for a matrix. A search coupled to the lookup table receives a clock size associated with a matrix and outputs parameters based upon the block size. A computation circuit coupled to receive the parameters outputs an address sequence using the parameters.

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Edinburgh, United Kingdom

Ben J Jones