Qlogic Corporation

Cavium, Inc.

Ben Hui

Dharma Konda

Rajendra R Gandhi

Bruce Anthony Klemin

Sanjaya Anand

Gregory J Goodemote

Methods and systems for generating interrupts are provided. One method includes maintaining an in-pointer array by a response direct memory access (DMA) module of an adapter indicating that a message has been posted at a host memory of a host system coupled to the adapter for sending and receiving data using a network; updating an out-pointer array at the response DMA module by a host system processor, after the host system processor reads the message posted at the host memory; receiving event information by a hardware based, interrupt module of the response DMA module, the interrupt module using the event information and information stored at an interrupt array to determine that an interrupt is to be generated for the host processor; and generating the interrupt for the host processor by the interrupt module, without using an adapter processor.

Methods and systems for generating interrupts by a response direct memory access module

Methods and systems for routing control blocks is provided. One method includes receiving a control block from a computing device at an adapter having a plurality of hardware engines for processing control blocks, where the control blocks are to read data, write data, obtain status for an input/output request and perform a management task; evaluating the control block by the adapter to determine that the control block is a continuation control block for data transfer using more than one control block; is a direct route control block for a specific hardware engine; or is for a management task; routing the control block to a same hardware engine when the control block is a continuation control block; and routing the control block to a master hardware engine from among the plurality of hardware engines, when the control block is for the management task.

Methods and systems for control block routing

A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.

Method and system for processing out of orders frames

A method and system processing non-data frames in a host bus adapter with a main processor and a first processor coupled to a host system and fibre channel is provided. The method includes, examining non-data frames; storing non-data frame information; notifying the first processor of non-data frames; and processing non-data frames without generating an interrupt for the main processor. The host bust adapter includes a fibre channel module ('FPM') with a state machine, wherein the fibre channel module receives and examines the non-data frames and stores non-data frame information in a FIFO. The FPM notifies the first processor that the non-data frames have been received.

Growing community of inventors

Irvine, CA, United States of America

Ben Hui