Nvidia Corporation

Ben Faulkner

Tezaswi Raja

Sachin Satish Idgunji

Tao Liu

Wen Yueh

Divya Ramakrishnan

Siddharth Saxena

Chad Plummer

Kartik Joshi

Vinayak Bhargav Srinath

Veeramani V

Ayon Dey

Javid Aziz

Introduced herein is an improved technique of recovering system frequency margin via distributed CPMs. The introduced technique creates and distributes multiple sets of always sensitized critical path replicas across a chip and monitors them for timing failure. The introduced technique takes feedback from these critical path replicas and dynamically boosts the clock frequency of the chip to remove the margin. The introduced technique provides more accurate and more comprehensive coverage of a chip performance.

System frequency margin recovery via distributed critical path monitors (CPM)

Aspects of the present invention are directed to techniques for improving the efficiency of power supply schemes by continuously and adaptively scaling voltage and frequency levels in an integrated circuit based on measured conditions in real-time, without resorting to a reliance on excessive pre-computed margins typical of conventional schemes. Embodiments of the present invention employ a self-tuning dynamic voltage control oscillator (or other similar clock signal generator) that sets the frequency for components in the integrated circuit. When a requested frequency exceeds a maximum allowed frequency for a given voltage level (accounting for other age and temperature related conditions), a look-up table is dynamically referenced to determine a new voltage level that is sufficient to safely and efficiently generate the requested frequency. The look-up table continuously receives updates on the operating conditions, and new voltage requests can be generated dynamically as necessary based on the system's current needs.

Adaptive voltage frequency scaling for optimal power efficiency

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Santa Clara, CA, United States of America

Ben Faulkner